Lines Matching refs:chip
22 * @regs: register offsets (NAND chip dependent)
49 * chip
60 static bool hynix_nand_has_valid_jedecid(struct nand_chip *chip)
65 ret = nand_readid_op(chip, 0x40, jedecid, sizeof(jedecid));
72 static int hynix_nand_cmd_op(struct nand_chip *chip, u8 cmd)
74 if (nand_has_exec_op(chip)) {
78 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
80 return nand_exec_op(chip, &op);
83 chip->legacy.cmdfunc(chip, cmd, -1, -1);
88 static int hynix_nand_reg_write_op(struct nand_chip *chip, u8 addr, u8 val)
92 if (nand_has_exec_op(chip)) {
97 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
99 return nand_exec_op(chip, &op);
102 chip->legacy.cmdfunc(chip, NAND_CMD_NONE, column, -1);
103 chip->legacy.write_byte(chip, val);
108 static int hynix_nand_setup_read_retry(struct nand_chip *chip, int retry_mode)
110 struct hynix_nand *hynix = nand_get_manufacturer_data(chip);
118 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_SET_PARAMS);
132 ret = hynix_nand_reg_write_op(chip, hynix->read_retry->regs[i],
139 return hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_APPLY_PARAMS);
191 static int hynix_read_rr_otp(struct nand_chip *chip,
197 ret = nand_reset_op(chip);
201 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_SET_PARAMS);
206 ret = hynix_nand_reg_write_op(chip, info->regs[i],
212 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_APPLY_PARAMS);
217 ret = hynix_nand_cmd_op(chip, 0x17);
221 ret = hynix_nand_cmd_op(chip, 0x4);
225 ret = hynix_nand_cmd_op(chip, 0x19);
230 ret = nand_read_page_op(chip, info->page, 0, buf, info->size);
235 ret = nand_reset_op(chip);
239 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_SET_PARAMS);
243 ret = hynix_nand_reg_write_op(chip, 0x38, 0);
247 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_APPLY_PARAMS);
251 return nand_read_page_op(chip, 0, 0, NULL, 0);
287 static int hynix_mlc_1xnm_rr_init(struct nand_chip *chip,
290 struct hynix_nand *hynix = nand_get_manufacturer_data(chip);
300 ret = hynix_read_rr_otp(chip, info, buf);
340 chip->ops.setup_read_retry = hynix_nand_setup_read_retry;
341 chip->read_retries = nmodes;
372 static int hynix_nand_rr_init(struct nand_chip *chip)
377 valid_jedecid = hynix_nand_has_valid_jedecid(chip);
384 u8 nand_tech = chip->id.data[5] >> 4;
394 ret = hynix_mlc_1xnm_rr_init(chip,
408 static void hynix_nand_extract_oobsize(struct nand_chip *chip,
411 struct mtd_info *mtd = nand_to_mtd(chip);
415 memorg = nanddev_get_memorg(&chip->base);
417 oobsize = ((chip->id.data[3] >> 2) & 0x3) |
418 ((chip->id.data[3] >> 4) & 0x4);
480 * Area Size" is encoded "per 8KB" (page size). This chip uses
484 * Update the OOB size for this chip by taking the value
486 * the actual OOB size for this chip is: 640 * 16k / 8k).
488 if (chip->id.data[1] == 0xde)
495 static void hynix_nand_extract_ecc_requirements(struct nand_chip *chip,
498 struct nand_device *base = &chip->base;
500 u8 ecc_level = (chip->id.data[4] >> 4) & 0x7;
543 u8 nand_tech = chip->id.data[5] & 0x7;
584 static void hynix_nand_extract_scrambling_requirements(struct nand_chip *chip,
590 if (nanddev_bits_per_cell(&chip->base) > 2)
591 chip->options |= NAND_NEED_SCRAMBLING;
595 nand_tech = chip->id.data[5] >> 4;
599 chip->options |= NAND_NEED_SCRAMBLING;
601 nand_tech = chip->id.data[5] & 0x7;
605 chip->options |= NAND_NEED_SCRAMBLING;
609 static void hynix_nand_decode_id(struct nand_chip *chip)
611 struct mtd_info *mtd = nand_to_mtd(chip);
616 memorg = nanddev_get_memorg(&chip->base);
625 if (chip->id.len < 6 || nand_is_slc(chip)) {
626 nand_decode_ext_id(chip);
631 memorg->pagesize = 2048 << (chip->id.data[3] & 0x03);
634 tmp = (chip->id.data[3] >> 4) & 0x3;
642 if (chip->id.data[3] & 0x80) {
661 valid_jedecid = hynix_nand_has_valid_jedecid(chip);
663 hynix_nand_extract_oobsize(chip, valid_jedecid);
664 hynix_nand_extract_ecc_requirements(chip, valid_jedecid);
665 hynix_nand_extract_scrambling_requirements(chip, valid_jedecid);
668 static void hynix_nand_cleanup(struct nand_chip *chip)
670 struct hynix_nand *hynix = nand_get_manufacturer_data(chip);
677 nand_set_manufacturer_data(chip, NULL);
681 h27ucg8t2atrbc_choose_interface_config(struct nand_chip *chip,
684 onfi_fill_interface_config(chip, iface, NAND_SDR_IFACE, 4);
686 return nand_choose_best_sdr_timings(chip, iface, NULL);
689 static int h27ucg8t2etrbc_init(struct nand_chip *chip)
691 struct mtd_info *mtd = nand_to_mtd(chip);
693 chip->options |= NAND_NEED_SCRAMBLING;
699 static int hynix_nand_init(struct nand_chip *chip)
704 if (!nand_is_slc(chip))
705 chip->options |= NAND_BBM_LASTPAGE;
707 chip->options |= NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE;
713 nand_set_manufacturer_data(chip, hynix);
715 if (!strncmp("H27UCG8T2ATR-BC", chip->parameters.model,
717 chip->ops.choose_interface_config =
720 if (!strncmp("H27UCG8T2ETR-BC", chip->parameters.model,
722 h27ucg8t2etrbc_init(chip);
724 ret = hynix_nand_rr_init(chip);
726 hynix_nand_cleanup(chip);
731 static void hynix_fixup_onfi_param_page(struct nand_chip *chip,