Lines Matching refs:chip
100 static int check_offs_len(struct nand_chip *chip, loff_t ofs, uint64_t len)
105 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
111 if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
165 * @chip: NAND chip object
166 * @cs: the CS line to select. Note that this CS id is always from the chip
169 * Select a NAND target so that further operations executed on @chip go to the
172 void nand_select_target(struct nand_chip *chip, unsigned int cs)
178 if (WARN_ON(cs > nanddev_ntargets(&chip->base)))
181 chip->cur_cs = cs;
183 if (chip->legacy.select_chip)
184 chip->legacy.select_chip(chip, cs);
190 * @chip: NAND chip object
193 * executed on @chip after the target has been deselected is undefined.
195 void nand_deselect_target(struct nand_chip *chip)
197 if (chip->legacy.select_chip)
198 chip->legacy.select_chip(chip, -1);
200 chip->cur_cs = -1;
205 * nand_release_device - [GENERIC] release chip
206 * @chip: NAND chip object
208 * Release chip lock and wake up anyone waiting on the device.
210 static void nand_release_device(struct nand_chip *chip)
212 /* Release the controller and the chip */
213 mutex_unlock(&chip->controller->lock);
214 mutex_unlock(&chip->lock);
219 * @chip: NAND chip object
226 int nand_bbm_get_next_page(struct nand_chip *chip, int page)
228 struct mtd_info *mtd = nand_to_mtd(chip);
230 chip->page_shift) & chip->pagemask;
234 if (page == 0 && !(chip->options & bbm_flags))
236 if (page == 0 && chip->options & NAND_BBM_FIRSTPAGE)
238 if (page <= 1 && chip->options & NAND_BBM_SECONDPAGE)
240 if (page <= last_page && chip->options & NAND_BBM_LASTPAGE)
247 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
248 * @chip: NAND chip object
253 static int nand_block_bad(struct nand_chip *chip, loff_t ofs)
259 first_page = (int)(ofs >> chip->page_shift) & chip->pagemask;
260 page_offset = nand_bbm_get_next_page(chip, 0);
263 res = chip->ecc.read_oob(chip, first_page + page_offset);
267 bad = chip->oob_poi[chip->badblockpos];
269 if (likely(chip->badblockbits == 8))
272 res = hweight8(bad) < chip->badblockbits;
276 page_offset = nand_bbm_get_next_page(chip, page_offset + 1);
284 * @chip: NAND chip object
292 static bool nand_region_is_secured(struct nand_chip *chip, loff_t offset, u64 size)
297 for (i = 0; i < chip->nr_secure_regions; i++) {
298 const struct nand_secure_region *region = &chip->secure_regions[i];
313 static int nand_isbad_bbm(struct nand_chip *chip, loff_t ofs)
315 struct mtd_info *mtd = nand_to_mtd(chip);
317 if (chip->options & NAND_NO_BBM_QUIRK)
321 if (nand_region_is_secured(chip, ofs, mtd->erasesize))
327 if (chip->legacy.block_bad)
328 return chip->legacy.block_bad(chip, ofs);
330 return nand_block_bad(chip, ofs);
334 * nand_get_device - [GENERIC] Get chip for selected access
335 * @chip: NAND chip structure
339 static void nand_get_device(struct nand_chip *chip)
343 mutex_lock(&chip->lock);
344 if (!chip->suspended) {
345 mutex_lock(&chip->controller->lock);
348 mutex_unlock(&chip->lock);
350 wait_event(chip->resume_wq, !chip->suspended);
355 * nand_check_wp - [GENERIC] check if the chip is write protected
356 * @chip: NAND chip object
361 static int nand_check_wp(struct nand_chip *chip)
367 if (chip->options & NAND_BROKEN_XD)
371 ret = nand_status_op(chip, &status);
380 * @chip: NAND chip object
385 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, size_t len,
388 struct mtd_info *mtd = nand_to_mtd(chip);
395 memset(chip->oob_poi, 0xff, mtd->oobsize);
401 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
405 ret = mtd_ooblayout_set_databytes(mtd, oob, chip->oob_poi,
418 * @chip: NAND chip object
424 static int nand_do_write_oob(struct nand_chip *chip, loff_t to,
427 struct mtd_info *mtd = nand_to_mtd(chip);
443 if (nand_region_is_secured(chip, to, ops->ooblen))
446 chipnr = (int)(to >> chip->chip_shift);
449 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
454 ret = nand_reset(chip, chipnr);
458 nand_select_target(chip, chipnr);
461 page = (int)(to >> chip->page_shift);
464 if (nand_check_wp(chip)) {
465 nand_deselect_target(chip);
470 if (page == chip->pagecache.page)
471 chip->pagecache.page = -1;
473 nand_fill_oob(chip, ops->oobbuf, ops->ooblen, ops);
476 status = chip->ecc.write_oob_raw(chip, page & chip->pagemask);
478 status = chip->ecc.write_oob(chip, page & chip->pagemask);
480 nand_deselect_target(chip);
492 * @chip: NAND chip object
499 static int nand_default_block_markbad(struct nand_chip *chip, loff_t ofs)
501 struct mtd_info *mtd = nand_to_mtd(chip);
508 ops.ooboffs = chip->badblockpos;
509 if (chip->options & NAND_BUSWIDTH_16) {
517 page_offset = nand_bbm_get_next_page(chip, 0);
520 res = nand_do_write_oob(chip,
527 page_offset = nand_bbm_get_next_page(chip, page_offset + 1);
535 * @chip: NAND chip object
538 int nand_markbad_bbm(struct nand_chip *chip, loff_t ofs)
540 if (chip->legacy.block_markbad)
541 return chip->legacy.block_markbad(chip, ofs);
543 return nand_default_block_markbad(chip, ofs);
548 * @chip: NAND chip object
553 * specify how to write bad block markers to OOB (chip->legacy.block_markbad).
565 static int nand_block_markbad_lowlevel(struct nand_chip *chip, loff_t ofs)
567 struct mtd_info *mtd = nand_to_mtd(chip);
570 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
576 einfo.len = 1ULL << chip->phys_erase_shift;
577 nand_erase_nand(chip, &einfo, 0);
580 nand_get_device(chip);
582 ret = nand_markbad_bbm(chip, ofs);
583 nand_release_device(chip);
587 if (chip->bbt) {
588 res = nand_markbad_bbt(chip, ofs);
608 struct nand_chip *chip = mtd_to_nand(mtd);
610 if (!chip->bbt)
613 return nand_isreserved_bbt(chip, ofs);
618 * @chip: NAND chip object
625 static int nand_block_checkbad(struct nand_chip *chip, loff_t ofs, int allowbbt)
628 if (chip->bbt)
629 return nand_isbad_bbt(chip, ofs, allowbbt);
631 return nand_isbad_bbm(chip, ofs);
636 * @chip: NAND chip structure
649 * Return 0 if the NAND chip is ready, a negative error otherwise.
651 int nand_soft_waitrdy(struct nand_chip *chip, unsigned long timeout_ms)
657 if (!nand_has_exec_op(chip))
661 conf = nand_get_interface_config(chip);
664 ret = nand_status_op(chip, NULL);
675 ret = nand_read_data_op(chip, &status, sizeof(status), true,
696 nand_exit_status_op(chip);
707 * @chip: NAND chip structure
717 * Return 0 if the R/B pin indicates chip is ready, a negative error otherwise.
719 int nand_gpio_waitrdy(struct nand_chip *chip, struct gpio_desc *gpiod,
724 * Wait until R/B pin indicates chip is ready or timeout occurs.
743 * @chip: NAND chip structure
750 void panic_nand_wait(struct nand_chip *chip, unsigned long timeo)
754 if (chip->legacy.dev_ready) {
755 if (chip->legacy.dev_ready(chip))
761 ret = nand_read_data_op(chip, &status, sizeof(status),
773 static bool nand_supports_get_features(struct nand_chip *chip, int addr)
775 return (chip->parameters.supports_set_get_features &&
776 test_bit(addr, chip->parameters.get_feature_list));
779 static bool nand_supports_set_features(struct nand_chip *chip, int addr)
781 return (chip->parameters.supports_set_get_features &&
782 test_bit(addr, chip->parameters.set_feature_list));
787 * @chip: The NAND chip
794 static int nand_reset_interface(struct nand_chip *chip, int chipnr)
796 const struct nand_controller_ops *ops = chip->controller->ops;
799 if (!nand_controller_can_setup_interface(chip))
816 chip->current_interface_config = nand_get_reset_interface_config();
817 ret = ops->setup_interface(chip, chipnr,
818 chip->current_interface_config);
827 * @chip: The NAND chip
831 * timings supported by the chip and the driver.
835 static int nand_setup_interface(struct nand_chip *chip, int chipnr)
837 const struct nand_controller_ops *ops = chip->controller->ops;
841 if (!nand_controller_can_setup_interface(chip))
845 * A nand_reset_interface() put both the NAND chip and the NAND
846 * controller in timings mode 0. If the default mode for this chip is
851 if (!chip->best_interface_config)
854 request = chip->best_interface_config->timings.mode;
855 if (nand_interface_is_sdr(chip->best_interface_config))
861 /* Change the mode on the chip side (if supported by the NAND chip) */
862 if (nand_supports_set_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE)) {
863 nand_select_target(chip, chipnr);
864 ret = nand_set_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE,
866 nand_deselect_target(chip);
872 ret = ops->setup_interface(chip, chipnr, chip->best_interface_config);
876 /* Check the mode has been accepted by the chip, if supported */
877 if (!nand_supports_get_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE))
881 nand_select_target(chip, chipnr);
882 ret = nand_get_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE,
884 nand_deselect_target(chip);
889 pr_warn("%s timing mode %d not acknowledged by the NAND chip\n",
890 nand_interface_is_nvddr(chip->best_interface_config) ? "NV-DDR" : "SDR",
891 chip->best_interface_config->timings.mode);
892 pr_debug("NAND chip would work in %s timing mode %d\n",
899 chip->current_interface_config = chip->best_interface_config;
905 * Fallback to mode 0 if the chip explicitly did not ack the chosen
908 nand_reset_interface(chip, chipnr);
909 nand_select_target(chip, chipnr);
910 nand_reset_op(chip);
911 nand_deselect_target(chip);
918 * NAND controller and the NAND chip support
919 * @chip: the NAND chip
926 int nand_choose_best_sdr_timings(struct nand_chip *chip,
930 const struct nand_controller_ops *ops = chip->controller->ops;
940 ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY,
943 chip->best_interface_config = iface;
949 } else if (chip->parameters.onfi) {
950 best_mode = fls(chip->parameters.onfi->sdr_timing_modes) - 1;
954 onfi_fill_interface_config(chip, iface, NAND_SDR_IFACE, mode);
956 ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY,
959 chip->best_interface_config = iface;
969 * NAND controller and the NAND chip support
970 * @chip: the NAND chip
977 int nand_choose_best_nvddr_timings(struct nand_chip *chip,
981 const struct nand_controller_ops *ops = chip->controller->ops;
991 ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY,
994 chip->best_interface_config = iface;
1000 } else if (chip->parameters.onfi) {
1001 best_mode = fls(chip->parameters.onfi->nvddr_timing_modes) - 1;
1005 onfi_fill_interface_config(chip, iface, NAND_NVDDR_IFACE, mode);
1007 ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY,
1010 chip->best_interface_config = iface;
1020 * NAND controller and the NAND chip support
1021 * @chip: the NAND chip
1027 static int nand_choose_best_timings(struct nand_chip *chip,
1033 ret = nand_choose_best_nvddr_timings(chip, iface, NULL);
1038 return nand_choose_best_sdr_timings(chip, iface, NULL);
1043 * @chip: The NAND chip
1045 * Find the best data interface and NAND timings supported by the chip
1054 static int nand_choose_interface_config(struct nand_chip *chip)
1059 if (!nand_controller_can_setup_interface(chip))
1066 if (chip->ops.choose_interface_config)
1067 ret = chip->ops.choose_interface_config(chip, iface);
1069 ret = nand_choose_best_timings(chip, iface);
1079 * @chip: The NAND chip
1089 static int nand_fill_column_cycles(struct nand_chip *chip, u8 *addrs,
1092 struct mtd_info *mtd = nand_to_mtd(chip);
1110 if (chip->options & NAND_BUSWIDTH_16) {
1131 static int nand_sp_exec_read_page_op(struct nand_chip *chip, unsigned int page,
1136 nand_get_interface_config(chip);
1137 struct mtd_info *mtd = nand_to_mtd(chip);
1146 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1156 !(chip->options & NAND_BUSWIDTH_16))
1159 ret = nand_fill_column_cycles(chip, addrs, offset_in_page);
1166 if (chip->options & NAND_ROW_ADDR_3) {
1171 return nand_exec_op(chip, &op);
1174 static int nand_lp_exec_read_page_op(struct nand_chip *chip, unsigned int page,
1179 nand_get_interface_config(chip);
1189 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1196 ret = nand_fill_column_cycles(chip, addrs, offset_in_page);
1203 if (chip->options & NAND_ROW_ADDR_3) {
1208 return nand_exec_op(chip, &op);
1211 static void rawnand_cap_cont_reads(struct nand_chip *chip)
1216 memorg = nanddev_get_memorg(&chip->base);
1218 first_lun = chip->cont_read.first_page / pages_per_lun;
1219 last_lun = chip->cont_read.last_page / pages_per_lun;
1223 chip->cont_read.pause_page = first_lun * pages_per_lun + pages_per_lun - 1;
1225 chip->cont_read.pause_page = chip->cont_read.last_page;
1228 static int nand_lp_exec_cont_read_page_op(struct nand_chip *chip, unsigned int page,
1233 nand_get_interface_config(chip);
1246 NAND_OP_CMD(page == chip->cont_read.pause_page ?
1253 struct nand_operation start_op = NAND_OPERATION(chip->cur_cs, start_instrs);
1254 struct nand_operation cont_op = NAND_OPERATION(chip->cur_cs, cont_instrs);
1262 ret = nand_fill_column_cycles(chip, addrs, offset_in_page);
1269 if (chip->options & NAND_ROW_ADDR_3) {
1276 if (nand_check_op(chip, &start_op) || nand_check_op(chip, &cont_op))
1282 if (page == chip->cont_read.first_page)
1283 ret = nand_exec_op(chip, &start_op);
1285 ret = nand_exec_op(chip, &cont_op);
1289 if (!chip->cont_read.ongoing)
1292 if (page == chip->cont_read.pause_page &&
1293 page != chip->cont_read.last_page) {
1294 chip->cont_read.first_page = chip->cont_read.pause_page + 1;
1295 rawnand_cap_cont_reads(chip);
1296 } else if (page == chip->cont_read.last_page) {
1297 chip->cont_read.ongoing = false;
1303 static bool rawnand_cont_read_ongoing(struct nand_chip *chip, unsigned int page)
1305 return chip->cont_read.ongoing && page >= chip->cont_read.first_page;
1310 * @chip: The NAND chip
1321 int nand_read_page_op(struct nand_chip *chip, unsigned int page,
1324 struct mtd_info *mtd = nand_to_mtd(chip);
1332 if (nand_has_exec_op(chip)) {
1334 if (rawnand_cont_read_ongoing(chip, page))
1335 return nand_lp_exec_cont_read_page_op(chip, page,
1339 return nand_lp_exec_read_page_op(chip, page,
1344 return nand_sp_exec_read_page_op(chip, page, offset_in_page,
1348 chip->legacy.cmdfunc(chip, NAND_CMD_READ0, offset_in_page, page);
1350 chip->legacy.read_buf(chip, buf, len);
1358 * @chip: The NAND chip
1368 int nand_read_param_page_op(struct nand_chip *chip, u8 page, void *buf,
1377 if (nand_has_exec_op(chip)) {
1379 nand_get_interface_config(chip);
1388 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1394 return nand_exec_op(chip, &op);
1397 chip->legacy.cmdfunc(chip, NAND_CMD_PARAM, page, -1);
1399 p[i] = chip->legacy.read_byte(chip);
1406 * @chip: The NAND chip
1417 int nand_change_read_column_op(struct nand_chip *chip,
1421 struct mtd_info *mtd = nand_to_mtd(chip);
1433 if (nand_has_exec_op(chip)) {
1435 nand_get_interface_config(chip);
1444 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1447 ret = nand_fill_column_cycles(chip, addrs, offset_in_page);
1457 return nand_exec_op(chip, &op);
1460 chip->legacy.cmdfunc(chip, NAND_CMD_RNDOUT, offset_in_page, -1);
1462 chip->legacy.read_buf(chip, buf, len);
1470 * @chip: The NAND chip
1481 int nand_read_oob_op(struct nand_chip *chip, unsigned int page,
1484 struct mtd_info *mtd = nand_to_mtd(chip);
1492 if (nand_has_exec_op(chip))
1493 return nand_read_page_op(chip, page,
1497 chip->legacy.cmdfunc(chip, NAND_CMD_READOOB, offset_in_oob, page);
1499 chip->legacy.read_buf(chip, buf, len);
1505 static int nand_exec_prog_page_op(struct nand_chip *chip, unsigned int page,
1510 nand_get_interface_config(chip);
1511 struct mtd_info *mtd = nand_to_mtd(chip);
1527 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1528 int naddrs = nand_fill_column_cycles(chip, addrs, offset_in_page);
1535 if (chip->options & NAND_ROW_ADDR_3)
1557 !(chip->options & NAND_BUSWIDTH_16))
1568 return nand_exec_op(chip, &op);
1573 * @chip: The NAND chip
1584 int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page,
1588 struct mtd_info *mtd = nand_to_mtd(chip);
1596 if (nand_has_exec_op(chip))
1597 return nand_exec_prog_page_op(chip, page, offset_in_page, buf,
1600 chip->legacy.cmdfunc(chip, NAND_CMD_SEQIN, offset_in_page, page);
1603 chip->legacy.write_buf(chip, buf, len);
1611 * @chip: The NAND chip
1618 int nand_prog_page_end_op(struct nand_chip *chip)
1623 if (nand_has_exec_op(chip)) {
1625 nand_get_interface_config(chip);
1632 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1634 ret = nand_exec_op(chip, &op);
1638 ret = nand_status_op(chip, &status);
1642 chip->legacy.cmdfunc(chip, NAND_CMD_PAGEPROG, -1, -1);
1643 ret = chip->legacy.waitfunc(chip);
1659 * @chip: The NAND chip
1670 int nand_prog_page_op(struct nand_chip *chip, unsigned int page,
1674 struct mtd_info *mtd = nand_to_mtd(chip);
1684 if (nand_has_exec_op(chip)) {
1685 ret = nand_exec_prog_page_op(chip, page, offset_in_page, buf,
1690 ret = nand_status_op(chip, &status);
1694 chip->legacy.cmdfunc(chip, NAND_CMD_SEQIN, offset_in_page,
1696 chip->legacy.write_buf(chip, buf, len);
1697 chip->legacy.cmdfunc(chip, NAND_CMD_PAGEPROG, -1, -1);
1698 ret = chip->legacy.waitfunc(chip);
1714 * @chip: The NAND chip
1725 int nand_change_write_column_op(struct nand_chip *chip,
1730 struct mtd_info *mtd = nand_to_mtd(chip);
1742 if (nand_has_exec_op(chip)) {
1744 nand_get_interface_config(chip);
1751 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1754 ret = nand_fill_column_cycles(chip, addrs, offset_in_page);
1764 return nand_exec_op(chip, &op);
1767 chip->legacy.cmdfunc(chip, NAND_CMD_RNDIN, offset_in_page, -1);
1769 chip->legacy.write_buf(chip, buf, len);
1777 * @chip: The NAND chip
1788 int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf,
1797 if (nand_has_exec_op(chip)) {
1799 nand_get_interface_config(chip);
1806 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1823 ret = nand_exec_op(chip, &op);
1834 chip->legacy.cmdfunc(chip, NAND_CMD_READID, addr, -1);
1837 id[i] = chip->legacy.read_byte(chip);
1845 * @chip: The NAND chip
1854 int nand_status_op(struct nand_chip *chip, u8 *status)
1856 if (nand_has_exec_op(chip)) {
1858 nand_get_interface_config(chip);
1865 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1877 ret = nand_exec_op(chip, &op);
1884 chip->legacy.cmdfunc(chip, NAND_CMD_STATUS, -1, -1);
1886 *status = chip->legacy.read_byte(chip);
1894 * @chip: The NAND chip
1903 int nand_exit_status_op(struct nand_chip *chip)
1905 if (nand_has_exec_op(chip)) {
1909 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1911 return nand_exec_op(chip, &op);
1914 chip->legacy.cmdfunc(chip, NAND_CMD_READ0, -1, -1);
1922 * @chip: The NAND chip
1931 int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock)
1934 (chip->phys_erase_shift - chip->page_shift);
1938 if (nand_has_exec_op(chip)) {
1940 nand_get_interface_config(chip);
1950 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1952 if (chip->options & NAND_ROW_ADDR_3)
1955 ret = nand_exec_op(chip, &op);
1959 ret = nand_status_op(chip, &status);
1963 chip->legacy.cmdfunc(chip, NAND_CMD_ERASE1, -1, page);
1964 chip->legacy.cmdfunc(chip, NAND_CMD_ERASE2, -1, -1);
1966 ret = chip->legacy.waitfunc(chip);
1982 * @chip: The NAND chip
1992 static int nand_set_features_op(struct nand_chip *chip, u8 feature,
1998 if (nand_has_exec_op(chip)) {
2000 nand_get_interface_config(chip);
2011 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
2013 return nand_exec_op(chip, &op);
2016 chip->legacy.cmdfunc(chip, NAND_CMD_SET_FEATURES, feature, -1);
2018 chip->legacy.write_byte(chip, params[i]);
2020 ret = chip->legacy.waitfunc(chip);
2032 * @chip: The NAND chip
2042 static int nand_get_features_op(struct nand_chip *chip, u8 feature,
2048 if (nand_has_exec_op(chip)) {
2050 nand_get_interface_config(chip);
2060 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
2069 ret = nand_exec_op(chip, &op);
2078 chip->legacy.cmdfunc(chip, NAND_CMD_GET_FEATURES, feature, -1);
2080 params[i] = chip->legacy.read_byte(chip);
2085 static int nand_wait_rdy_op(struct nand_chip *chip, unsigned int timeout_ms,
2088 if (nand_has_exec_op(chip)) {
2093 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
2095 return nand_exec_op(chip, &op);
2099 if (!chip->legacy.dev_ready)
2100 udelay(chip->legacy.chip_delay);
2102 nand_wait_ready(chip);
2109 * @chip: The NAND chip
2117 int nand_reset_op(struct nand_chip *chip)
2119 if (nand_has_exec_op(chip)) {
2121 nand_get_interface_config(chip);
2128 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
2130 return nand_exec_op(chip, &op);
2133 chip->legacy.cmdfunc(chip, NAND_CMD_RESET, -1, -1);
2141 * @chip: The NAND chip
2154 int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len,
2160 if (nand_has_exec_op(chip)) {
2162 nand_get_interface_config(chip);
2166 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
2189 ret = nand_check_op(chip, &op);
2194 ret = nand_exec_op(chip, &op);
2215 p[i] = chip->legacy.read_byte(chip);
2217 chip->legacy.read_buf(chip, buf, len);
2226 * @chip: The NAND chip
2237 int nand_write_data_op(struct nand_chip *chip, const void *buf,
2243 if (nand_has_exec_op(chip)) {
2247 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
2251 return nand_exec_op(chip, &op);
2259 chip->legacy.write_byte(chip, p[i]);
2261 chip->legacy.write_buf(chip, buf, len);
2469 * @chip: the NAND chip
2489 int nand_op_parser_exec_op(struct nand_chip *chip,
2531 ret = pattern->exec(chip, &ctx.subop);
2682 * @chip: The NAND chip
2691 int nand_reset(struct nand_chip *chip, int chipnr)
2695 ret = nand_reset_interface(chip, chipnr);
2704 nand_select_target(chip, chipnr);
2705 ret = nand_reset_op(chip);
2706 nand_deselect_target(chip);
2710 ret = nand_setup_interface(chip, chipnr);
2720 * @chip: NAND chip info structure
2727 int nand_get_features(struct nand_chip *chip, int addr,
2730 if (!nand_supports_get_features(chip, addr))
2733 if (chip->legacy.get_features)
2734 return chip->legacy.get_features(chip, addr, subfeature_param);
2736 return nand_get_features_op(chip, addr, subfeature_param);
2741 * @chip: NAND chip info structure
2748 int nand_set_features(struct nand_chip *chip, int addr,
2751 if (!nand_supports_set_features(chip, addr))
2754 if (chip->legacy.set_features)
2755 return chip->legacy.set_features(chip, addr, subfeature_param);
2757 return nand_set_features_op(chip, addr, subfeature_param);
2893 * @chip: nand chip info structure
2895 * @oob_required: caller requires OOB data read to chip->oob_poi
2900 int nand_read_page_raw_notsupp(struct nand_chip *chip, u8 *buf,
2908 * @chip: nand chip info structure
2910 * @oob_required: caller requires OOB data read to chip->oob_poi
2915 int nand_read_page_raw(struct nand_chip *chip, uint8_t *buf, int oob_required,
2918 struct mtd_info *mtd = nand_to_mtd(chip);
2921 ret = nand_read_page_op(chip, page, 0, buf, mtd->writesize);
2926 ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize,
2938 * @chip: NAND chip info structure
2940 * @oob_required: caller requires OOB data read to chip->oob_poi
2946 * bus (from the NAND chip to the NAND controller) in a single
2951 int nand_monolithic_read_page_raw(struct nand_chip *chip, u8 *buf,
2954 struct mtd_info *mtd = nand_to_mtd(chip);
2962 if (buf != chip->data_buf)
2963 read_buf = nand_get_data_buf(chip);
2966 ret = nand_read_page_op(chip, page, 0, read_buf, size);
2970 if (buf != chip->data_buf)
2979 * @chip: nand chip info structure
2981 * @oob_required: caller requires OOB data read to chip->oob_poi
2986 static int nand_read_page_raw_syndrome(struct nand_chip *chip, uint8_t *buf,
2989 struct mtd_info *mtd = nand_to_mtd(chip);
2990 int eccsize = chip->ecc.size;
2991 int eccbytes = chip->ecc.bytes;
2992 uint8_t *oob = chip->oob_poi;
2995 ret = nand_read_page_op(chip, page, 0, NULL, 0);
2999 for (steps = chip->ecc.steps; steps > 0; steps--) {
3000 ret = nand_read_data_op(chip, buf, eccsize, false, false);
3006 if (chip->ecc.prepad) {
3007 ret = nand_read_data_op(chip, oob, chip->ecc.prepad,
3012 oob += chip->ecc.prepad;
3015 ret = nand_read_data_op(chip, oob, eccbytes, false, false);
3021 if (chip->ecc.postpad) {
3022 ret = nand_read_data_op(chip, oob, chip->ecc.postpad,
3027 oob += chip->ecc.postpad;
3031 size = mtd->oobsize - (oob - chip->oob_poi);
3033 ret = nand_read_data_op(chip, oob, size, false, false);
3043 * @chip: nand chip info structure
3045 * @oob_required: caller requires OOB data read to chip->oob_poi
3048 static int nand_read_page_swecc(struct nand_chip *chip, uint8_t *buf,
3051 struct mtd_info *mtd = nand_to_mtd(chip);
3052 int i, eccsize = chip->ecc.size, ret;
3053 int eccbytes = chip->ecc.bytes;
3054 int eccsteps = chip->ecc.steps;
3056 uint8_t *ecc_calc = chip->ecc.calc_buf;
3057 uint8_t *ecc_code = chip->ecc.code_buf;
3060 chip->ecc.read_page_raw(chip, buf, 1, page);
3063 chip->ecc.calculate(chip, p, &ecc_calc[i]);
3065 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
3066 chip->ecc.total);
3070 eccsteps = chip->ecc.steps;
3076 stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]);
3089 * @chip: nand chip info structure
3095 static int nand_read_subpage(struct nand_chip *chip, uint32_t data_offs,
3098 struct mtd_info *mtd = nand_to_mtd(chip);
3103 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
3109 start_step = data_offs / chip->ecc.size;
3110 end_step = (data_offs + readlen - 1) / chip->ecc.size;
3112 index = start_step * chip->ecc.bytes;
3115 datafrag_len = num_steps * chip->ecc.size;
3116 eccfrag_len = num_steps * chip->ecc.bytes;
3118 data_col_addr = start_step * chip->ecc.size;
3121 ret = nand_read_page_op(chip, page, data_col_addr, p, datafrag_len);
3126 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
3127 chip->ecc.calculate(chip, p, &chip->ecc.calc_buf[i]);
3141 ret = nand_change_read_column_op(chip, mtd->writesize,
3142 chip->oob_poi, mtd->oobsize,
3155 if ((oobregion.offset + (num_steps * chip->ecc.bytes)) &
3159 ret = nand_change_read_column_op(chip,
3161 &chip->oob_poi[aligned_pos],
3167 ret = mtd_ooblayout_get_eccbytes(mtd, chip->ecc.code_buf,
3168 chip->oob_poi, index, eccfrag_len);
3173 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
3176 stat = chip->ecc.correct(chip, p, &chip->ecc.code_buf[i],
3177 &chip->ecc.calc_buf[i]);
3179 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
3181 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
3182 &chip->ecc.code_buf[i],
3183 chip->ecc.bytes,
3185 chip->ecc.strength);
3200 * @chip: nand chip info structure
3202 * @oob_required: caller requires OOB data read to chip->oob_poi
3207 static int nand_read_page_hwecc(struct nand_chip *chip, uint8_t *buf,
3210 struct mtd_info *mtd = nand_to_mtd(chip);
3211 int i, eccsize = chip->ecc.size, ret;
3212 int eccbytes = chip->ecc.bytes;
3213 int eccsteps = chip->ecc.steps;
3215 uint8_t *ecc_calc = chip->ecc.calc_buf;
3216 uint8_t *ecc_code = chip->ecc.code_buf;
3219 ret = nand_read_page_op(chip, page, 0, NULL, 0);
3224 chip->ecc.hwctl(chip, NAND_ECC_READ);
3226 ret = nand_read_data_op(chip, p, eccsize, false, false);
3230 chip->ecc.calculate(chip, p, &ecc_calc[i]);
3233 ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, false,
3238 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
3239 chip->ecc.total);
3243 eccsteps = chip->ecc.steps;
3249 stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]);
3251 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
3256 chip->ecc.strength);
3272 * @chip: nand chip info structure
3274 * @oob_required: caller requires OOB data read to chip->oob_poi
3280 int nand_read_page_hwecc_oob_first(struct nand_chip *chip, uint8_t *buf,
3283 struct mtd_info *mtd = nand_to_mtd(chip);
3284 int i, eccsize = chip->ecc.size, ret;
3285 int eccbytes = chip->ecc.bytes;
3286 int eccsteps = chip->ecc.steps;
3288 uint8_t *ecc_code = chip->ecc.code_buf;
3292 ret = nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
3297 ret = nand_change_read_column_op(chip, 0, NULL, 0, false);
3301 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
3302 chip->ecc.total);
3309 chip->ecc.hwctl(chip, NAND_ECC_READ);
3311 ret = nand_read_data_op(chip, p, eccsize, false, false);
3315 stat = chip->ecc.correct(chip, p, &ecc_code[i], NULL);
3317 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
3322 chip->ecc.strength);
3338 * @chip: nand chip info structure
3340 * @oob_required: caller requires OOB data read to chip->oob_poi
3346 static int nand_read_page_syndrome(struct nand_chip *chip, uint8_t *buf,
3349 struct mtd_info *mtd = nand_to_mtd(chip);
3350 int ret, i, eccsize = chip->ecc.size;
3351 int eccbytes = chip->ecc.bytes;
3352 int eccsteps = chip->ecc.steps;
3353 int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
3355 uint8_t *oob = chip->oob_poi;
3358 ret = nand_read_page_op(chip, page, 0, NULL, 0);
3365 chip->ecc.hwctl(chip, NAND_ECC_READ);
3367 ret = nand_read_data_op(chip, p, eccsize, false, false);
3371 if (chip->ecc.prepad) {
3372 ret = nand_read_data_op(chip, oob, chip->ecc.prepad,
3377 oob += chip->ecc.prepad;
3380 chip->ecc.hwctl(chip, NAND_ECC_READSYN);
3382 ret = nand_read_data_op(chip, oob, eccbytes, false, false);
3386 stat = chip->ecc.correct(chip, p, oob, NULL);
3390 if (chip->ecc.postpad) {
3391 ret = nand_read_data_op(chip, oob, chip->ecc.postpad,
3396 oob += chip->ecc.postpad;
3400 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
3402 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
3406 chip->ecc.strength);
3418 i = mtd->oobsize - (oob - chip->oob_poi);
3420 ret = nand_read_data_op(chip, oob, i, false, false);
3430 * @chip: NAND chip object
3435 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
3438 struct mtd_info *mtd = nand_to_mtd(chip);
3445 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
3449 ret = mtd_ooblayout_get_databytes(mtd, oob, chip->oob_poi,
3460 static void rawnand_enable_cont_reads(struct nand_chip *chip, unsigned int page,
3463 struct mtd_info *mtd = nand_to_mtd(chip);
3466 chip->cont_read.ongoing = false;
3468 if (!chip->controller->supported_op.cont_read)
3483 chip->cont_read.first_page = page;
3484 chip->cont_read.last_page = end_page;
3485 chip->cont_read.ongoing = true;
3487 rawnand_cap_cont_reads(chip);
3490 static void rawnand_cont_read_skip_first_page(struct nand_chip *chip, unsigned int page)
3492 if (!chip->cont_read.ongoing || page != chip->cont_read.first_page)
3495 chip->cont_read.first_page++;
3496 if (chip->cont_read.first_page == chip->cont_read.pause_page)
3497 chip->cont_read.first_page++;
3498 if (chip->cont_read.first_page >= chip->cont_read.last_page)
3499 chip->cont_read.ongoing = false;
3504 * @chip: NAND chip object
3511 static int nand_setup_read_retry(struct nand_chip *chip, int retry_mode)
3515 if (retry_mode >= chip->read_retries)
3518 if (!chip->ops.setup_read_retry)
3521 return chip->ops.setup_read_retry(chip, retry_mode);
3524 static void nand_wait_readrdy(struct nand_chip *chip)
3528 if (!(chip->options & NAND_NEED_READRDY))
3531 conf = nand_get_interface_config(chip);
3532 WARN_ON(nand_wait_rdy_op(chip, NAND_COMMON_TIMING_MS(conf, tR_max), 0));
3537 * @chip: NAND chip object
3541 * Internal function. Called with chip held.
3543 static int nand_do_read_ops(struct nand_chip *chip, loff_t from,
3547 struct mtd_info *mtd = nand_to_mtd(chip);
3560 if (nand_region_is_secured(chip, from, readlen))
3563 chipnr = (int)(from >> chip->chip_shift);
3564 nand_select_target(chip, chipnr);
3566 realpage = (int)(from >> chip->page_shift);
3567 page = realpage & chip->pagemask;
3575 rawnand_enable_cont_reads(chip, page, readlen, col);
3585 else if (chip->options & NAND_USES_DMA)
3588 chip->buf_align);
3593 if (realpage != chip->pagecache.page || oob) {
3594 bufpoi = use_bounce_buf ? chip->data_buf : buf;
3606 ret = chip->ecc.read_page_raw(chip, bufpoi,
3609 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
3611 ret = chip->ecc.read_subpage(chip, col, bytes,
3614 ret = chip->ecc.read_page(chip, bufpoi,
3619 chip->pagecache.page = -1;
3628 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
3631 chip->pagecache.page = realpage;
3632 chip->pagecache.bitflips = ret;
3635 chip->pagecache.page = -1;
3644 oob = nand_transfer_oob(chip, oob, ops,
3650 nand_wait_readrdy(chip);
3653 if (retry_mode + 1 < chip->read_retries) {
3655 ret = nand_setup_read_retry(chip,
3672 memcpy(buf, chip->data_buf + col, bytes);
3675 chip->pagecache.bitflips);
3677 rawnand_cont_read_skip_first_page(chip, page);
3684 ret = nand_setup_read_retry(chip, 0);
3698 page = realpage & chip->pagemask;
3699 /* Check, if we cross a chip boundary */
3702 nand_deselect_target(chip);
3703 nand_select_target(chip, chipnr);
3706 nand_deselect_target(chip);
3723 * @chip: nand chip info structure
3726 int nand_read_oob_std(struct nand_chip *chip, int page)
3728 struct mtd_info *mtd = nand_to_mtd(chip);
3730 return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
3737 * @chip: nand chip info structure
3740 static int nand_read_oob_syndrome(struct nand_chip *chip, int page)
3742 struct mtd_info *mtd = nand_to_mtd(chip);
3744 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
3745 int eccsize = chip->ecc.size;
3746 uint8_t *bufpoi = chip->oob_poi;
3749 ret = nand_read_page_op(chip, page, chip->ecc.size, NULL, 0);
3753 for (i = 0; i < chip->ecc.steps; i++) {
3759 ret = nand_change_read_column_op(chip, pos,
3763 ret = nand_read_page_op(chip, page, pos, NULL,
3772 ret = nand_read_data_op(chip, bufpoi, toread, false, false);
3780 ret = nand_read_data_op(chip, bufpoi, length, false, false);
3790 * @chip: nand chip info structure
3793 int nand_write_oob_std(struct nand_chip *chip, int page)
3795 struct mtd_info *mtd = nand_to_mtd(chip);
3797 return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi,
3805 * @chip: nand chip info structure
3808 static int nand_write_oob_syndrome(struct nand_chip *chip, int page)
3810 struct mtd_info *mtd = nand_to_mtd(chip);
3811 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
3812 int eccsize = chip->ecc.size, length = mtd->oobsize;
3813 int ret, i, len, pos, sndcmd = 0, steps = chip->ecc.steps;
3814 const uint8_t *bufpoi = chip->oob_poi;
3821 if (!chip->ecc.prepad && !chip->ecc.postpad) {
3827 ret = nand_prog_page_begin_op(chip, page, pos, NULL, 0);
3840 ret = nand_write_data_op(chip, &fill,
3849 ret = nand_change_write_column_op(chip, pos,
3859 ret = nand_write_data_op(chip, bufpoi, len, false);
3867 ret = nand_write_data_op(chip, bufpoi, length, false);
3872 return nand_prog_page_end_op(chip);
3877 * @chip: NAND chip object
3883 static int nand_do_read_oob(struct nand_chip *chip, loff_t from,
3886 struct mtd_info *mtd = nand_to_mtd(chip);
3899 if (nand_region_is_secured(chip, from, readlen))
3906 chipnr = (int)(from >> chip->chip_shift);
3907 nand_select_target(chip, chipnr);
3910 realpage = (int)(from >> chip->page_shift);
3911 page = realpage & chip->pagemask;
3915 ret = chip->ecc.read_oob_raw(chip, page);
3917 ret = chip->ecc.read_oob(chip, page);
3923 buf = nand_transfer_oob(chip, buf, ops, len);
3925 nand_wait_readrdy(chip);
3936 page = realpage & chip->pagemask;
3937 /* Check, if we cross a chip boundary */
3940 nand_deselect_target(chip);
3941 nand_select_target(chip, chipnr);
3944 nand_deselect_target(chip);
3968 struct nand_chip *chip = mtd_to_nand(mtd);
3979 nand_get_device(chip);
3984 ret = nand_do_read_oob(chip, from, ops);
3986 ret = nand_do_read_ops(chip, from, ops);
3995 nand_release_device(chip);
4001 * @chip: nand chip info structure
4003 * @oob_required: must write chip->oob_poi to OOB
4008 int nand_write_page_raw_notsupp(struct nand_chip *chip, const u8 *buf,
4016 * @chip: nand chip info structure
4018 * @oob_required: must write chip->oob_poi to OOB
4023 int nand_write_page_raw(struct nand_chip *chip, const uint8_t *buf,
4026 struct mtd_info *mtd = nand_to_mtd(chip);
4029 ret = nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize);
4034 ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize,
4040 return nand_prog_page_end_op(chip);
4046 * @chip: NAND chip info structure
4048 * @oob_required: must write chip->oob_poi to OOB
4054 * into the NAND chip arrays in a single operation. This is an
4058 * synchronyze the NAND chip cache.
4060 int nand_monolithic_write_page_raw(struct nand_chip *chip, const u8 *buf,
4063 struct mtd_info *mtd = nand_to_mtd(chip);
4070 if (buf != chip->data_buf) {
4071 write_buf = nand_get_data_buf(chip);
4076 return nand_prog_page_op(chip, page, 0, write_buf, size);
4082 * @chip: nand chip info structure
4084 * @oob_required: must write chip->oob_poi to OOB
4089 static int nand_write_page_raw_syndrome(struct nand_chip *chip,
4093 struct mtd_info *mtd = nand_to_mtd(chip);
4094 int eccsize = chip->ecc.size;
4095 int eccbytes = chip->ecc.bytes;
4096 uint8_t *oob = chip->oob_poi;
4099 ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0);
4103 for (steps = chip->ecc.steps; steps > 0; steps--) {
4104 ret = nand_write_data_op(chip, buf, eccsize, false);
4110 if (chip->ecc.prepad) {
4111 ret = nand_write_data_op(chip, oob, chip->ecc.prepad,
4116 oob += chip->ecc.prepad;
4119 ret = nand_write_data_op(chip, oob, eccbytes, false);
4125 if (chip->ecc.postpad) {
4126 ret = nand_write_data_op(chip, oob, chip->ecc.postpad,
4131 oob += chip->ecc.postpad;
4135 size = mtd->oobsize - (oob - chip->oob_poi);
4137 ret = nand_write_data_op(chip, oob, size, false);
4142 return nand_prog_page_end_op(chip);
4146 * @chip: nand chip info structure
4148 * @oob_required: must write chip->oob_poi to OOB
4151 static int nand_write_page_swecc(struct nand_chip *chip, const uint8_t *buf,
4154 struct mtd_info *mtd = nand_to_mtd(chip);
4155 int i, eccsize = chip->ecc.size, ret;
4156 int eccbytes = chip->ecc.bytes;
4157 int eccsteps = chip->ecc.steps;
4158 uint8_t *ecc_calc = chip->ecc.calc_buf;
4163 chip->ecc.calculate(chip, p, &ecc_calc[i]);
4165 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
4166 chip->ecc.total);
4170 return chip->ecc.write_page_raw(chip, buf, 1, page);
4175 * @chip: nand chip info structure
4177 * @oob_required: must write chip->oob_poi to OOB
4180 static int nand_write_page_hwecc(struct nand_chip *chip, const uint8_t *buf,
4183 struct mtd_info *mtd = nand_to_mtd(chip);
4184 int i, eccsize = chip->ecc.size, ret;
4185 int eccbytes = chip->ecc.bytes;
4186 int eccsteps = chip->ecc.steps;
4187 uint8_t *ecc_calc = chip->ecc.calc_buf;
4190 ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0);
4195 chip->ecc.hwctl(chip, NAND_ECC_WRITE);
4197 ret = nand_write_data_op(chip, p, eccsize, false);
4201 chip->ecc.calculate(chip, p, &ecc_calc[i]);
4204 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
4205 chip->ecc.total);
4209 ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);
4213 return nand_prog_page_end_op(chip);
4219 * @chip: nand chip info structure
4223 * @oob_required: must write chip->oob_poi to OOB
4226 static int nand_write_subpage_hwecc(struct nand_chip *chip, uint32_t offset,
4230 struct mtd_info *mtd = nand_to_mtd(chip);
4231 uint8_t *oob_buf = chip->oob_poi;
4232 uint8_t *ecc_calc = chip->ecc.calc_buf;
4233 int ecc_size = chip->ecc.size;
4234 int ecc_bytes = chip->ecc.bytes;
4235 int ecc_steps = chip->ecc.steps;
4241 ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0);
4247 chip->ecc.hwctl(chip, NAND_ECC_WRITE);
4250 ret = nand_write_data_op(chip, buf, ecc_size, false);
4258 chip->ecc.calculate(chip, buf, ecc_calc);
4270 /* copy calculated ECC for whole page to chip->buffer->oob */
4272 ecc_calc = chip->ecc.calc_buf;
4273 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
4274 chip->ecc.total);
4279 ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);
4283 return nand_prog_page_end_op(chip);
4289 * @chip: nand chip info structure
4291 * @oob_required: must write chip->oob_poi to OOB
4297 static int nand_write_page_syndrome(struct nand_chip *chip, const uint8_t *buf,
4300 struct mtd_info *mtd = nand_to_mtd(chip);
4301 int i, eccsize = chip->ecc.size;
4302 int eccbytes = chip->ecc.bytes;
4303 int eccsteps = chip->ecc.steps;
4305 uint8_t *oob = chip->oob_poi;
4308 ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0);
4313 chip->ecc.hwctl(chip, NAND_ECC_WRITE);
4315 ret = nand_write_data_op(chip, p, eccsize, false);
4319 if (chip->ecc.prepad) {
4320 ret = nand_write_data_op(chip, oob, chip->ecc.prepad,
4325 oob += chip->ecc.prepad;
4328 chip->ecc.calculate(chip, p, oob);
4330 ret = nand_write_data_op(chip, oob, eccbytes, false);
4336 if (chip->ecc.postpad) {
4337 ret = nand_write_data_op(chip, oob, chip->ecc.postpad,
4342 oob += chip->ecc.postpad;
4347 i = mtd->oobsize - (oob - chip->oob_poi);
4349 ret = nand_write_data_op(chip, oob, i, false);
4354 return nand_prog_page_end_op(chip);
4359 * @chip: NAND chip descriptor
4363 * @oob_required: must write chip->oob_poi to OOB
4367 static int nand_write_page(struct nand_chip *chip, uint32_t offset,
4371 struct mtd_info *mtd = nand_to_mtd(chip);
4374 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
4375 chip->ecc.write_subpage)
4381 status = chip->ecc.write_page_raw(chip, buf, oob_required,
4384 status = chip->ecc.write_subpage(chip, offset, data_len, buf,
4387 status = chip->ecc.write_page(chip, buf, oob_required, page);
4395 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
4399 * @chip: NAND chip object
4405 static int nand_do_write_ops(struct nand_chip *chip, loff_t to,
4408 struct mtd_info *mtd = nand_to_mtd(chip);
4432 if (nand_region_is_secured(chip, to, writelen))
4437 chipnr = (int)(to >> chip->chip_shift);
4438 nand_select_target(chip, chipnr);
4441 if (nand_check_wp(chip)) {
4446 realpage = (int)(to >> chip->page_shift);
4447 page = realpage & chip->pagemask;
4450 if (to <= ((loff_t)chip->pagecache.page << chip->page_shift) &&
4451 ((loff_t)chip->pagecache.page << chip->page_shift) < (to + ops->len))
4452 chip->pagecache.page = -1;
4468 else if (chip->options & NAND_USES_DMA)
4471 chip->buf_align);
4484 wbuf = nand_get_data_buf(chip);
4491 oob = nand_fill_oob(chip, oob, len, ops);
4495 memset(chip->oob_poi, 0xff, mtd->oobsize);
4498 ret = nand_write_page(chip, column, bytes, wbuf,
4512 page = realpage & chip->pagemask;
4513 /* Check, if we cross a chip boundary */
4516 nand_deselect_target(chip);
4517 nand_select_target(chip, chipnr);
4526 nand_deselect_target(chip);
4544 struct nand_chip *chip = mtd_to_nand(mtd);
4545 int chipnr = (int)(to >> chip->chip_shift);
4549 nand_select_target(chip, chipnr);
4552 panic_nand_wait(chip, 400);
4559 ret = nand_do_write_ops(chip, to, &ops);
4574 struct nand_chip *chip = mtd_to_nand(mtd);
4579 nand_get_device(chip);
4592 ret = nand_do_write_oob(chip, to, ops);
4594 ret = nand_do_write_ops(chip, to, ops);
4597 nand_release_device(chip);
4615 * @chip: NAND chip object
4621 int nand_erase_nand(struct nand_chip *chip, struct erase_info *instr,
4631 if (check_offs_len(chip, instr->addr, instr->len))
4635 if (nand_region_is_secured(chip, instr->addr, instr->len))
4639 nand_get_device(chip);
4642 page = (int)(instr->addr >> chip->page_shift);
4643 chipnr = (int)(instr->addr >> chip->chip_shift);
4646 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
4649 nand_select_target(chip, chipnr);
4652 if (nand_check_wp(chip)) {
4663 loff_t ofs = (loff_t)page << chip->page_shift;
4666 if (nand_block_checkbad(chip, ((loff_t) page) <<
4667 chip->page_shift, allowbbt)) {
4678 if (page <= chip->pagecache.page && chip->pagecache.page <
4680 chip->pagecache.page = -1;
4682 ret = nand_erase_op(chip, (page & chip->pagemask) >>
4683 (chip->phys_erase_shift - chip->page_shift));
4692 len -= (1ULL << chip->phys_erase_shift);
4695 /* Check, if we cross a chip boundary */
4696 if (len && !(page & chip->pagemask)) {
4698 nand_deselect_target(chip);
4699 nand_select_target(chip, chipnr);
4707 nand_deselect_target(chip);
4708 nand_release_device(chip);
4718 * Sync is actually a wait for chip ready function.
4722 struct nand_chip *chip = mtd_to_nand(mtd);
4727 nand_get_device(chip);
4729 nand_release_device(chip);
4739 struct nand_chip *chip = mtd_to_nand(mtd);
4740 int chipnr = (int)(offs >> chip->chip_shift);
4744 nand_get_device(chip);
4746 nand_select_target(chip, chipnr);
4748 ret = nand_block_checkbad(chip, offs, 0);
4750 nand_deselect_target(chip);
4751 nand_release_device(chip);
4784 struct nand_chip *chip = mtd_to_nand(mtd);
4787 mutex_lock(&chip->lock);
4788 if (chip->ops.suspend)
4789 ret = chip->ops.suspend(chip);
4791 chip->suspended = 1;
4792 mutex_unlock(&chip->lock);
4803 struct nand_chip *chip = mtd_to_nand(mtd);
4805 mutex_lock(&chip->lock);
4806 if (chip->suspended) {
4807 if (chip->ops.resume)
4808 chip->ops.resume(chip);
4809 chip->suspended = 0;
4811 pr_err("%s called for a chip which is not in suspended state\n",
4814 mutex_unlock(&chip->lock);
4816 wake_up_all(&chip->resume_wq);
4837 struct nand_chip *chip = mtd_to_nand(mtd);
4839 if (!chip->ops.lock_area)
4842 return chip->ops.lock_area(chip, ofs, len);
4853 struct nand_chip *chip = mtd_to_nand(mtd);
4855 if (!chip->ops.unlock_area)
4858 return chip->ops.unlock_area(chip, ofs, len);
4862 static void nand_set_defaults(struct nand_chip *chip)
4865 if (!chip->controller) {
4866 chip->controller = &chip->legacy.dummy_controller;
4867 nand_controller_init(chip->controller);
4870 nand_legacy_set_defaults(chip);
4872 if (!chip->buf_align)
4873 chip->buf_align = 1;
4965 * chip. The rest of the parameters must be decoded according to generic or
4968 void nand_decode_ext_id(struct nand_chip *chip)
4971 struct mtd_info *mtd = nand_to_mtd(chip);
4973 u8 *id_data = chip->id.data;
4975 memorg = nanddev_get_memorg(&chip->base);
4997 chip->options |= NAND_BUSWIDTH_16;
5002 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
5004 * the chip.
5006 static void nand_decode_id(struct nand_chip *chip, struct nand_flash_dev *type)
5008 struct mtd_info *mtd = nand_to_mtd(chip);
5011 memorg = nanddev_get_memorg(&chip->base);
5029 static void nand_decode_bbm_options(struct nand_chip *chip)
5031 struct mtd_info *mtd = nand_to_mtd(chip);
5034 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
5035 chip->badblockpos = NAND_BBM_POS_LARGE;
5037 chip->badblockpos = NAND_BBM_POS_SMALL;
5045 static bool find_full_id_nand(struct nand_chip *chip,
5048 struct nand_device *base = &chip->base;
5050 struct mtd_info *mtd = nand_to_mtd(chip);
5052 u8 *id_data = chip->id.data;
5054 memorg = nanddev_get_memorg(&chip->base);
5070 chip->options |= type->options;
5075 chip->parameters.model = kstrdup(type->name, GFP_KERNEL);
5076 if (!chip->parameters.model)
5089 static void nand_manufacturer_detect(struct nand_chip *chip)
5095 if (chip->manufacturer.desc && chip->manufacturer.desc->ops &&
5096 chip->manufacturer.desc->ops->detect) {
5099 memorg = nanddev_get_memorg(&chip->base);
5102 memorg->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]);
5103 chip->manufacturer.desc->ops->detect(chip);
5105 nand_decode_ext_id(chip);
5115 static int nand_manufacturer_init(struct nand_chip *chip)
5117 if (!chip->manufacturer.desc || !chip->manufacturer.desc->ops ||
5118 !chip->manufacturer.desc->ops->init)
5121 return chip->manufacturer.desc->ops->init(chip);
5130 static void nand_manufacturer_cleanup(struct nand_chip *chip)
5133 if (chip->manufacturer.desc && chip->manufacturer.desc->ops &&
5134 chip->manufacturer.desc->ops->cleanup)
5135 chip->manufacturer.desc->ops->cleanup(chip);
5144 static void rawnand_check_data_only_read_support(struct nand_chip *chip)
5147 if (!nand_read_data_op(chip, NULL, SZ_512, true, true))
5148 chip->controller->supported_op.data_only_read = 1;
5151 static void rawnand_early_check_supported_ops(struct nand_chip *chip)
5154 WARN_ON_ONCE(chip->controller->supported_op.data_only_read);
5156 if (!nand_has_exec_op(chip))
5159 rawnand_check_data_only_read_support(chip);
5162 static void rawnand_check_cont_read_support(struct nand_chip *chip)
5164 struct mtd_info *mtd = nand_to_mtd(chip);
5166 if (!chip->parameters.supports_read_cache)
5169 if (chip->read_retries)
5172 if (!nand_lp_exec_cont_read_page_op(chip, 0, 0, NULL,
5174 chip->controller->supported_op.cont_read = 1;
5177 static void rawnand_late_check_supported_ops(struct nand_chip *chip)
5180 WARN_ON_ONCE(chip->controller->supported_op.cont_read);
5187 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_DIE)
5190 if (!nand_has_exec_op(chip))
5193 rawnand_check_cont_read_support(chip);
5199 static int nand_detect(struct nand_chip *chip, struct nand_flash_dev *type)
5202 struct mtd_info *mtd = nand_to_mtd(chip);
5205 u8 *id_data = chip->id.data;
5213 memorg = nanddev_get_memorg(&chip->base);
5218 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
5221 ret = nand_reset(chip, 0);
5226 nand_select_target(chip, 0);
5228 rawnand_early_check_supported_ops(chip);
5231 ret = nand_readid_op(chip, 0, id_data, 2);
5247 ret = nand_readid_op(chip, 0, id_data, sizeof(chip->id.data));
5257 chip->id.len = nand_id_len(id_data, ARRAY_SIZE(chip->id.data));
5261 chip->manufacturer.desc = manufacturer_desc;
5273 busw = chip->options & NAND_BUSWIDTH_16;
5279 chip->options &= ~NAND_BUSWIDTH_16;
5283 if (find_full_id_nand(chip, type))
5291 /* Check if the chip is ONFI compliant */
5292 ret = nand_onfi_detect(chip);
5298 /* Check if the chip is JEDEC compliant */
5299 ret = nand_jedec_detect(chip);
5309 chip->parameters.model = kstrdup(type->name, GFP_KERNEL);
5310 if (!chip->parameters.model)
5314 nand_manufacturer_detect(chip);
5316 nand_decode_id(chip, type);
5318 /* Get chip options */
5319 chip->options |= type->options;
5328 mtd->name = chip->parameters.model;
5330 if (chip->options & NAND_BUSWIDTH_AUTO) {
5332 nand_set_defaults(chip);
5333 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
5336 * chip correct!
5343 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8);
5349 nand_decode_bbm_options(chip);
5352 chip->page_shift = ffs(mtd->writesize) - 1;
5353 /* Convert chipsize to number of pages per chip -1 */
5354 targetsize = nanddev_target_size(&chip->base);
5355 chip->pagemask = (targetsize >> chip->page_shift) - 1;
5357 chip->bbt_erase_shift = chip->phys_erase_shift =
5360 chip->chip_shift = ffs((unsigned)targetsize) - 1;
5362 chip->chip_shift = ffs((unsigned)(targetsize >> 32));
5363 chip->chip_shift += 32 - 1;
5366 if (chip->chip_shift - chip->page_shift > 16)
5367 chip->options |= NAND_ROW_ADDR_3;
5369 chip->badblockbits = 8;
5371 nand_legacy_adjust_cmdfunc(chip);
5376 chip->parameters.model);
5378 (int)(targetsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
5383 kfree(chip->parameters.model);
5470 static void of_get_nand_ecc_legacy_user_config(struct nand_chip *chip)
5472 struct device_node *dn = nand_get_flash_node(chip);
5473 struct nand_ecc_props *user_conf = &chip->base.ecc.user_conf;
5485 static int of_get_nand_bus_width(struct nand_chip *chip)
5487 struct device_node *dn = nand_get_flash_node(chip);
5499 chip->options |= NAND_BUSWIDTH_16;
5505 static int of_get_nand_secure_regions(struct nand_chip *chip)
5507 struct device_node *dn = nand_get_flash_node(chip);
5520 chip->nr_secure_regions = nr_elem / 2;
5521 chip->secure_regions = kcalloc(chip->nr_secure_regions, sizeof(*chip->secure_regions),
5523 if (!chip->secure_regions)
5526 for (i = 0, j = 0; i < chip->nr_secure_regions; i++, j += 2) {
5528 &chip->secure_regions[i].offset);
5530 &chip->secure_regions[i].size);
5573 static int rawnand_dt_init(struct nand_chip *chip)
5575 struct nand_device *nand = mtd_to_nanddev(nand_to_mtd(chip));
5576 struct device_node *dn = nand_get_flash_node(chip);
5582 ret = of_get_nand_bus_width(chip);
5587 chip->options |= NAND_IS_BOOT_MEDIUM;
5590 chip->bbt_options |= NAND_BBT_USE_FLASH;
5593 of_get_nand_ecc_legacy_user_config(chip);
5607 chip->ecc.engine_type = nand->ecc.user_conf.engine_type;
5608 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_INVALID)
5609 chip->ecc.engine_type = nand->ecc.defaults.engine_type;
5611 chip->ecc.placement = nand->ecc.user_conf.placement;
5612 chip->ecc.algo = nand->ecc.user_conf.algo;
5613 chip->ecc.strength = nand->ecc.user_conf.strength;
5614 chip->ecc.size = nand->ecc.user_conf.step_size;
5621 * @chip: NAND chip object
5633 static int nand_scan_ident(struct nand_chip *chip, unsigned int maxchips,
5636 struct mtd_info *mtd = nand_to_mtd(chip);
5642 memorg = nanddev_get_memorg(&chip->base);
5645 chip->cur_cs = -1;
5647 mutex_init(&chip->lock);
5648 init_waitqueue_head(&chip->resume_wq);
5651 chip->current_interface_config = nand_get_reset_interface_config();
5653 ret = rawnand_dt_init(chip);
5661 nand_set_defaults(chip);
5663 ret = nand_legacy_check_hooks(chip);
5670 ret = nand_detect(chip, table);
5672 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
5674 nand_deselect_target(chip);
5678 nand_maf_id = chip->id.data[0];
5679 nand_dev_id = chip->id.data[1];
5681 nand_deselect_target(chip);
5683 /* Check for a chip array */
5688 ret = nand_reset(chip, i);
5692 nand_select_target(chip, i);
5694 ret = nand_readid_op(chip, 0, id, sizeof(id));
5699 nand_deselect_target(chip);
5702 nand_deselect_target(chip);
5709 mtd->size = i * nanddev_target_size(&chip->base);
5714 static void nand_scan_ident_cleanup(struct nand_chip *chip)
5716 kfree(chip->parameters.model);
5717 kfree(chip->parameters.onfi);
5720 int rawnand_sw_hamming_init(struct nand_chip *chip)
5723 struct nand_device *base = &chip->base;
5728 base->ecc.user_conf.strength = chip->ecc.strength;
5729 base->ecc.user_conf.step_size = chip->ecc.size;
5737 if (chip->ecc.options & NAND_ECC_SOFT_HAMMING_SM_ORDER)
5740 chip->ecc.size = base->ecc.ctx.conf.step_size;
5741 chip->ecc.strength = base->ecc.ctx.conf.strength;
5742 chip->ecc.total = base->ecc.ctx.total;
5743 chip->ecc.steps = nanddev_get_ecc_nsteps(base);
5744 chip->ecc.bytes = base->ecc.ctx.total / nanddev_get_ecc_nsteps(base);
5750 int rawnand_sw_hamming_calculate(struct nand_chip *chip,
5754 struct nand_device *base = &chip->base;
5760 int rawnand_sw_hamming_correct(struct nand_chip *chip,
5765 struct nand_device *base = &chip->base;
5771 void rawnand_sw_hamming_cleanup(struct nand_chip *chip)
5773 struct nand_device *base = &chip->base;
5779 int rawnand_sw_bch_init(struct nand_chip *chip)
5781 struct nand_device *base = &chip->base;
5787 base->ecc.user_conf.step_size = chip->ecc.size;
5788 base->ecc.user_conf.strength = chip->ecc.strength;
5794 chip->ecc.size = ecc_conf->step_size;
5795 chip->ecc.strength = ecc_conf->strength;
5796 chip->ecc.total = base->ecc.ctx.total;
5797 chip->ecc.steps = nanddev_get_ecc_nsteps(base);
5798 chip->ecc.bytes = base->ecc.ctx.total / nanddev_get_ecc_nsteps(base);
5804 static int rawnand_sw_bch_calculate(struct nand_chip *chip,
5808 struct nand_device *base = &chip->base;
5813 int rawnand_sw_bch_correct(struct nand_chip *chip, unsigned char *buf,
5816 struct nand_device *base = &chip->base;
5822 void rawnand_sw_bch_cleanup(struct nand_chip *chip)
5824 struct nand_device *base = &chip->base;
5830 static int nand_set_ecc_on_host_ops(struct nand_chip *chip)
5832 struct nand_ecc_ctrl *ecc = &chip->ecc;
5889 static int nand_set_ecc_soft_ops(struct nand_chip *chip)
5891 struct mtd_info *mtd = nand_to_mtd(chip);
5893 struct nand_ecc_ctrl *ecc = &chip->ecc;
5920 ret = rawnand_sw_hamming_init(chip);
5953 ret = rawnand_sw_bch_init(chip);
5968 * @chip: nand chip info structure
5973 * by the controller and the calculated ECC bytes fit within the chip's OOB.
5977 nand_check_ecc_caps(struct nand_chip *chip,
5980 struct mtd_info *mtd = nand_to_mtd(chip);
5982 int preset_step = chip->ecc.size;
5983 int preset_strength = chip->ecc.strength;
6008 chip->ecc.bytes = ecc_bytes;
6021 * nand_match_ecc_req - meet the chip's requirement with least ECC bytes
6022 * @chip: nand chip info structure
6026 * If a chip's ECC requirement is provided, try to meet it with the least
6031 nand_match_ecc_req(struct nand_chip *chip,
6035 nanddev_get_ecc_requirements(&chip->base);
6036 struct mtd_info *mtd = nand_to_mtd(chip);
6045 /* No information provided by the NAND chip */
6049 /* number of correctable bits the chip requires in a page */
6061 * chip's requirement, it is not easy to compare the
6082 * We assume the best is to meet the chip's requrement
6097 chip->ecc.size = best_step;
6098 chip->ecc.strength = best_strength;
6099 chip->ecc.bytes = best_ecc_bytes;
6106 * @chip: nand chip info structure
6111 * within the chip's OOB. On success, the chosen ECC settings are set.
6114 nand_maximize_ecc(struct nand_chip *chip,
6117 struct mtd_info *mtd = nand_to_mtd(chip);
6129 /* If chip->ecc.size is already set, respect it */
6130 if (chip->ecc.size && step_size != chip->ecc.size)
6167 chip->ecc.size = best_step;
6168 chip->ecc.strength = best_strength;
6169 chip->ecc.bytes = best_ecc_bytes;
6176 * @chip: nand chip info structure
6187 * to the chip's requirement. If available OOB size can't fit the chip
6192 int nand_ecc_choose_conf(struct nand_chip *chip,
6195 struct mtd_info *mtd = nand_to_mtd(chip);
6201 if (chip->ecc.size && chip->ecc.strength)
6202 return nand_check_ecc_caps(chip, caps, oobavail);
6205 return nand_maximize_ecc(chip, caps, oobavail);
6207 if (!nand_match_ecc_req(chip, caps, oobavail))
6210 return nand_maximize_ecc(chip, caps, oobavail);
6216 struct nand_chip *chip = container_of(nand, struct nand_chip,
6223 nand_select_target(chip, pos->target);
6224 ret = nand_erase_op(chip, eb);
6225 nand_deselect_target(chip);
6233 struct nand_chip *chip = container_of(nand, struct nand_chip,
6236 return nand_markbad_bbm(chip, nanddev_pos_to_offs(nand, pos));
6241 struct nand_chip *chip = container_of(nand, struct nand_chip,
6245 nand_select_target(chip, pos->target);
6246 ret = nand_isbad_bbm(chip, nanddev_pos_to_offs(nand, pos));
6247 nand_deselect_target(chip);
6260 * @chip: NAND chip object
6266 static int nand_scan_tail(struct nand_chip *chip)
6268 struct mtd_info *mtd = nand_to_mtd(chip);
6269 struct nand_ecc_ctrl *ecc = &chip->ecc;
6273 if (WARN_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
6274 !(chip->bbt_options & NAND_BBT_USE_FLASH))) {
6278 chip->data_buf = kmalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL);
6279 if (!chip->data_buf)
6286 * chip.
6288 nand_select_target(chip, 0);
6289 ret = nand_manufacturer_init(chip);
6290 nand_deselect_target(chip);
6295 chip->oob_poi = chip->data_buf + mtd->writesize;
6343 ret = nand_set_ecc_on_host_ops(chip);
6362 ret = nand_set_ecc_soft_ops(chip);
6431 chip->base.ecc.ctx.total = ecc->total;
6451 if (!nand_ecc_is_strong_enough(&chip->base))
6452 pr_warn("WARNING: %s: the ECC used on your system (%db/%dB) is too weak compared to the one required by the NAND chip (%db/%dB)\n",
6453 mtd->name, chip->ecc.strength, chip->ecc.size,
6454 nanddev_get_ecc_requirements(&chip->base)->strength,
6455 nanddev_get_ecc_requirements(&chip->base)->step_size);
6458 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
6470 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
6473 chip->pagecache.page = -1;
6478 if (chip->page_shift > 9)
6479 chip->options |= NAND_SUBPAGE_READ;
6486 ret = nanddev_init(&chip->base, &rawnand_ops, mtd->owner);
6491 if (chip->options & NAND_ROM)
6520 /* Find the fastest data interface for this chip */
6521 ret = nand_choose_interface_config(chip);
6526 for (i = 0; i < nanddev_ntargets(&chip->base); i++) {
6527 ret = nand_setup_interface(chip, i);
6532 rawnand_late_check_supported_ops(chip);
6535 * Look for secure regions in the NAND chip. These regions are supposed
6540 ret = of_get_nand_secure_regions(chip);
6545 if (chip->options & NAND_SKIP_BBTSCAN)
6549 ret = nand_create_bbt(chip);
6556 kfree(chip->secure_regions);
6559 kfree(chip->best_interface_config);
6562 nanddev_cleanup(&chip->base);
6565 nand_manufacturer_cleanup(chip);
6568 kfree(chip->data_buf);
6575 static int nand_attach(struct nand_chip *chip)
6577 if (chip->controller->ops && chip->controller->ops->attach_chip)
6578 return chip->controller->ops->attach_chip(chip);
6583 static void nand_detach(struct nand_chip *chip)
6585 if (chip->controller->ops && chip->controller->ops->detach_chip)
6586 chip->controller->ops->detach_chip(chip);
6591 * @chip: NAND chip object
6596 * The flash ID is read and the mtd/chip structures are filled with the
6599 int nand_scan_with_ids(struct nand_chip *chip, unsigned int maxchips,
6607 ret = nand_scan_ident(chip, maxchips, ids);
6611 ret = nand_attach(chip);
6615 ret = nand_scan_tail(chip);
6622 nand_detach(chip);
6624 nand_scan_ident_cleanup(chip);
6632 * @chip: NAND chip object
6634 void nand_cleanup(struct nand_chip *chip)
6636 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT) {
6637 if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING)
6638 rawnand_sw_hamming_cleanup(chip);
6639 else if (chip->ecc.algo == NAND_ECC_ALGO_BCH)
6640 rawnand_sw_bch_cleanup(chip);
6643 nanddev_cleanup(&chip->base);
6646 kfree(chip->secure_regions);
6649 kfree(chip->bbt);
6650 kfree(chip->data_buf);
6651 kfree(chip->ecc.code_buf);
6652 kfree(chip->ecc.calc_buf);
6655 if (chip->badblock_pattern && chip->badblock_pattern->options
6657 kfree(chip->badblock_pattern);
6660 kfree(chip->best_interface_config);
6663 nand_manufacturer_cleanup(chip);
6665 /* Free controller specific allocations after chip identification */
6666 nand_detach(chip);
6669 nand_scan_ident_cleanup(chip);