Lines Matching defs:ecc
126 int (*read_page)(struct nand_chip *chip, void *buf, void *oob, bool ecc,
669 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
687 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
711 bool ecc, int page)
719 host->devtype_data->enable_hwecc(chip, ecc);
744 if (buf && ecc) {
769 void *oob, bool ecc, int page)
778 host->devtype_data->enable_hwecc(chip, ecc);
853 bool ecc, int page)
858 host->devtype_data->enable_hwecc(chip, ecc);
1007 if (section >= nand_chip->ecc.steps)
1021 if (section > nand_chip->ecc.steps)
1034 if (section < nand_chip->ecc.steps)
1045 .ecc = mxc_v1_ooblayout_ecc,
1053 int stepsize = nand_chip->ecc.bytes == 9 ? 16 : 26;
1055 if (section >= nand_chip->ecc.steps)
1059 oobregion->length = nand_chip->ecc.bytes;
1068 int stepsize = nand_chip->ecc.bytes == 9 ? 16 : 26;
1070 if (section >= nand_chip->ecc.steps)
1090 .ecc = mxc_v2_ooblayout_ecc,
1095 * v2 and v3 type controllers can do 4bit or 8bit ecc depending
1096 * on how much oob the nand chip has. For 8bit ecc we need at least
1117 if (nand_chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST &&
1228 if (nand_chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST)
1304 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST)
1433 * The generic flash bbt descriptors overlap with our ecc
1617 chip->ecc.bytes = host->devtype_data->eccbytes;
1619 chip->ecc.size = 512;
1622 switch (chip->ecc.engine_type) {
1624 chip->ecc.read_page = mxc_nand_read_page;
1625 chip->ecc.read_page_raw = mxc_nand_read_page_raw;
1626 chip->ecc.read_oob = mxc_nand_read_oob;
1627 chip->ecc.write_page = mxc_nand_write_page_ecc;
1628 chip->ecc.write_page_raw = mxc_nand_write_page_raw;
1629 chip->ecc.write_oob = mxc_nand_write_oob;
1654 if (!chip->ecc.bytes) {
1656 chip->ecc.bytes = 18;
1658 chip->ecc.bytes = 9;
1670 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) {
1672 chip->ecc.strength = 1;
1674 chip->ecc.strength = (host->eccsize == 4) ? 4 : 8;