Lines Matching refs:nfc
259 struct meson_nfc *nfc = nand_get_controller_data(nand);
265 nfc->param.chip_select = meson_chip->sels[chip] ? NAND_CE1 : NAND_CE0;
266 nfc->param.rb_select = nfc->param.chip_select;
267 nfc->timing.twb = meson_chip->twb;
268 nfc->timing.tadl = meson_chip->tadl;
269 nfc->timing.tbers_max = meson_chip->tbers_max;
271 if (nfc->clk_rate != meson_chip->clk_rate) {
272 ret = clk_set_rate(nfc->nand_clk, meson_chip->clk_rate);
274 dev_err(nfc->dev, "failed to set clock rate\n");
277 nfc->clk_rate = meson_chip->clk_rate;
279 if (nfc->bus_timing != meson_chip->bus_timing) {
281 writel(value, nfc->reg_base + NFC_REG_CFG);
282 writel((1 << 31), nfc->reg_base + NFC_REG_CMD);
283 nfc->bus_timing = meson_chip->bus_timing;
287 static void meson_nfc_cmd_idle(struct meson_nfc *nfc, u32 time)
289 writel(nfc->param.chip_select | NFC_CMD_IDLE | (time & 0x3ff),
290 nfc->reg_base + NFC_REG_CMD);
293 static void meson_nfc_cmd_seed(struct meson_nfc *nfc, u32 seed)
296 nfc->reg_base + NFC_REG_CMD);
303 struct meson_nfc *nfc = nand_get_controller_data(mtd_to_nand(mtd));
313 writel(cmd, nfc->reg_base + NFC_REG_CMD);
322 writel(cmd, nfc->reg_base + NFC_REG_CMD);
325 static void meson_nfc_drain_cmd(struct meson_nfc *nfc)
338 meson_nfc_cmd_idle(nfc, 0);
339 meson_nfc_cmd_idle(nfc, 0);
342 static int meson_nfc_wait_cmd_finish(struct meson_nfc *nfc,
349 ret = readl_relaxed_poll_timeout(nfc->reg_base + NFC_REG_CMD, cmd_size,
353 dev_err(nfc->dev, "wait for empty CMD FIFO time out\n");
358 static int meson_nfc_wait_dma_finish(struct meson_nfc *nfc)
360 meson_nfc_drain_cmd(nfc);
362 return meson_nfc_wait_cmd_finish(nfc, DMA_BUSY_TIMEOUT);
427 struct meson_nfc *nfc = nand_get_controller_data(nand);
430 meson_nfc_cmd_idle(nfc, nfc->timing.twb);
431 meson_nfc_drain_cmd(nfc);
432 meson_nfc_wait_cmd_finish(nfc, CMD_FIFO_EMPTY_TIMEOUT);
434 cfg = readl(nfc->reg_base + NFC_REG_CFG);
436 writel(cfg, nfc->reg_base + NFC_REG_CFG);
438 reinit_completion(&nfc->completion);
442 cmd = NFC_CMD_RB | NFC_CMD_RB_INT_NO_PIN | nfc->timing.tbers_max;
443 writel(cmd, nfc->reg_base + NFC_REG_CMD);
445 if (!wait_for_completion_timeout(&nfc->completion,
455 static int meson_nfc_wait_rb_pin(struct meson_nfc *nfc, int timeout_ms)
460 meson_nfc_cmd_idle(nfc, nfc->timing.twb);
461 meson_nfc_drain_cmd(nfc);
462 meson_nfc_wait_cmd_finish(nfc, CMD_FIFO_EMPTY_TIMEOUT);
464 cfg = readl(nfc->reg_base + NFC_REG_CFG);
466 writel(cfg, nfc->reg_base + NFC_REG_CFG);
468 reinit_completion(&nfc->completion);
472 | nfc->param.chip_select | nfc->timing.tbers_max;
473 writel(cmd, nfc->reg_base + NFC_REG_CMD);
475 ret = wait_for_completion_timeout(&nfc->completion,
486 struct meson_nfc *nfc = nand_get_controller_data(nand);
488 if (nfc->no_rb_pin) {
502 return meson_nfc_wait_rb_pin(nfc, timeout_ms);
565 struct meson_nfc *nfc = nand_get_controller_data(nand);
569 nfc->daddr = dma_map_single(nfc->dev, databuf, datalen, dir);
570 ret = dma_mapping_error(nfc->dev, nfc->daddr);
572 dev_err(nfc->dev, "DMA mapping error\n");
575 cmd = GENCMDDADDRL(NFC_CMD_ADL, nfc->daddr);
576 writel(cmd, nfc->reg_base + NFC_REG_CMD);
578 cmd = GENCMDDADDRH(NFC_CMD_ADH, nfc->daddr);
579 writel(cmd, nfc->reg_base + NFC_REG_CMD);
582 nfc->iaddr = dma_map_single(nfc->dev, infobuf, infolen, dir);
583 ret = dma_mapping_error(nfc->dev, nfc->iaddr);
585 dev_err(nfc->dev, "DMA mapping error\n");
586 dma_unmap_single(nfc->dev,
587 nfc->daddr, datalen, dir);
590 nfc->info_bytes = infolen;
591 cmd = GENCMDIADDRL(NFC_CMD_AIL, nfc->iaddr);
592 writel(cmd, nfc->reg_base + NFC_REG_CMD);
594 cmd = GENCMDIADDRH(NFC_CMD_AIH, nfc->iaddr);
595 writel(cmd, nfc->reg_base + NFC_REG_CMD);
605 struct meson_nfc *nfc = nand_get_controller_data(nand);
607 dma_unmap_single(nfc->dev, nfc->daddr, datalen, dir);
609 dma_unmap_single(nfc->dev, nfc->iaddr, infolen, dir);
610 nfc->info_bytes = 0;
616 struct meson_nfc *nfc = nand_get_controller_data(nand);
631 writel(cmd, nfc->reg_base + NFC_REG_CMD);
633 meson_nfc_drain_cmd(nfc);
634 meson_nfc_wait_cmd_finish(nfc, 1000);
645 struct meson_nfc *nfc = nand_get_controller_data(nand);
655 writel(cmd, nfc->reg_base + NFC_REG_CMD);
657 meson_nfc_drain_cmd(nfc);
658 meson_nfc_wait_cmd_finish(nfc, 1000);
670 struct meson_nfc *nfc = nand_get_controller_data(nand);
671 u32 *addrs = nfc->cmdfifo.rw.addrs;
672 u32 cs = nfc->param.chip_select;
679 nfc->cmdfifo.rw.cmd0 = cs | NFC_CMD_CLE | cmd0;
703 writel_relaxed(nfc->cmdfifo.cmd[i],
704 nfc->reg_base + NFC_REG_CMD);
707 nfc->cmdfifo.rw.cmd1 = cs | NFC_CMD_CLE | NAND_CMD_READSTART;
708 writel(nfc->cmdfifo.rw.cmd1, nfc->reg_base + NFC_REG_CMD);
711 meson_nfc_cmd_idle(nfc, nfc->timing.tadl);
724 struct meson_nfc *nfc = nand_get_controller_data(nand);
745 meson_nfc_cmd_seed(nfc, page);
753 cmd = nfc->param.chip_select | NFC_CMD_CLE | NAND_CMD_PAGEPROG;
754 writel(cmd, nfc->reg_base + NFC_REG_CMD);
786 static void meson_nfc_check_ecc_pages_valid(struct meson_nfc *nfc,
798 /* info is updated by nfc dma engine*/
800 dma_sync_single_for_cpu(nfc->dev, nfc->iaddr, nfc->info_bytes,
810 struct meson_nfc *nfc = nand_get_controller_data(nand);
831 meson_nfc_cmd_seed(nfc, page);
839 ret = meson_nfc_wait_dma_finish(nfc);
840 meson_nfc_check_ecc_pages_valid(nfc, nand, raw);
1017 struct meson_nfc *nfc = nand_get_controller_data(nand);
1039 cmd = nfc->param.chip_select | NFC_CMD_CLE;
1041 writel(cmd, nfc->reg_base + NFC_REG_CMD);
1042 meson_nfc_cmd_idle(nfc, delay_idle);
1047 cmd = nfc->param.chip_select | NFC_CMD_ALE;
1049 writel(cmd, nfc->reg_base + NFC_REG_CMD);
1051 meson_nfc_cmd_idle(nfc, delay_idle);
1074 meson_nfc_cmd_idle(nfc, delay_idle);
1078 meson_nfc_wait_cmd_finish(nfc, 1000);
1115 static int meson_nfc_clk_init(struct meson_nfc *nfc)
1122 nfc->core_clk = devm_clk_get(nfc->dev, "core");
1123 if (IS_ERR(nfc->core_clk)) {
1124 dev_err(nfc->dev, "failed to get core clock\n");
1125 return PTR_ERR(nfc->core_clk);
1128 nfc->device_clk = devm_clk_get(nfc->dev, "device");
1129 if (IS_ERR(nfc->device_clk)) {
1130 dev_err(nfc->dev, "failed to get device clock\n");
1131 return PTR_ERR(nfc->device_clk);
1134 init.name = devm_kasprintf(nfc->dev,
1136 dev_name(nfc->dev));
1144 nfc->nand_divider.reg = nfc->reg_clk;
1145 nfc->nand_divider.shift = CLK_DIV_SHIFT;
1146 nfc->nand_divider.width = CLK_DIV_WIDTH;
1147 nfc->nand_divider.hw.init = &init;
1148 nfc->nand_divider.flags = CLK_DIVIDER_ONE_BASED |
1152 nfc->nand_clk = devm_clk_register(nfc->dev, &nfc->nand_divider.hw);
1153 if (IS_ERR(nfc->nand_clk))
1154 return PTR_ERR(nfc->nand_clk);
1157 writel(CLK_SELECT_NAND | readl(nfc->reg_clk),
1158 nfc->reg_clk);
1160 ret = clk_prepare_enable(nfc->core_clk);
1162 dev_err(nfc->dev, "failed to enable core clock\n");
1166 ret = clk_prepare_enable(nfc->device_clk);
1168 dev_err(nfc->dev, "failed to enable device clock\n");
1172 ret = clk_prepare_enable(nfc->nand_clk);
1174 dev_err(nfc->dev, "pre enable NFC divider fail\n");
1178 ret = clk_set_rate(nfc->nand_clk, 24000000);
1185 clk_disable_unprepare(nfc->nand_clk);
1187 clk_disable_unprepare(nfc->device_clk);
1189 clk_disable_unprepare(nfc->core_clk);
1193 static void meson_nfc_disable_clk(struct meson_nfc *nfc)
1195 clk_disable_unprepare(nfc->nand_clk);
1196 clk_disable_unprepare(nfc->device_clk);
1197 clk_disable_unprepare(nfc->core_clk);
1301 struct meson_nfc *nfc = nand_get_controller_data(nand);
1308 mtd->name = devm_kasprintf(nfc->dev, GFP_KERNEL,
1310 dev_name(nfc->dev),
1318 dev_err(nfc->dev, "too big write size in raw mode: %d > %ld\n",
1328 ret = nand_ecc_choose_conf(nand, nfc->data->ecc_caps,
1331 dev_err(nfc->dev, "failed to ECC init\n");
1353 dev_err(nfc->dev, "16bits bus width not supported");
1372 struct meson_nfc *nfc, struct device_node *np)
1402 if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
1409 nand->controller = &nfc->controller;
1412 nand_set_controller_data(nand, nfc);
1421 nfc->no_rb_pin = true;
1439 list_add_tail(&meson_chip->node, &nfc->chips);
1444 static void meson_nfc_nand_chip_cleanup(struct meson_nfc *nfc)
1449 while (!list_empty(&nfc->chips)) {
1450 meson_chip = list_first_entry(&nfc->chips,
1461 struct meson_nfc *nfc)
1468 ret = meson_nfc_nand_chip_init(dev, nfc, nand_np);
1470 meson_nfc_nand_chip_cleanup(nfc);
1481 struct meson_nfc *nfc = id;
1484 cfg = readl(nfc->reg_base + NFC_REG_CFG);
1489 writel(cfg, nfc->reg_base + NFC_REG_CFG);
1491 complete(&nfc->completion);
1505 .compatible = "amlogic,meson-gxl-nfc",
1508 .compatible = "amlogic,meson-axg-nfc",
1518 struct meson_nfc *nfc;
1521 nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
1522 if (!nfc)
1525 nfc->data = of_device_get_match_data(&pdev->dev);
1526 if (!nfc->data)
1529 nand_controller_init(&nfc->controller);
1530 INIT_LIST_HEAD(&nfc->chips);
1531 init_completion(&nfc->completion);
1533 nfc->dev = dev;
1535 nfc->reg_base = devm_platform_ioremap_resource_byname(pdev, "nfc");
1536 if (IS_ERR(nfc->reg_base))
1537 return PTR_ERR(nfc->reg_base);
1539 nfc->reg_clk = devm_platform_ioremap_resource_byname(pdev, "emmc");
1540 if (IS_ERR(nfc->reg_clk))
1541 return PTR_ERR(nfc->reg_clk);
1547 ret = meson_nfc_clk_init(nfc);
1553 writel(0, nfc->reg_base + NFC_REG_CFG);
1554 ret = devm_request_irq(dev, irq, meson_nfc_irq, 0, dev_name(dev), nfc);
1567 platform_set_drvdata(pdev, nfc);
1569 ret = meson_nfc_nand_chips_init(dev, nfc);
1577 meson_nfc_disable_clk(nfc);
1583 struct meson_nfc *nfc = platform_get_drvdata(pdev);
1585 meson_nfc_nand_chip_cleanup(nfc);
1587 meson_nfc_disable_clk(nfc);