Lines Matching refs:NDCR
125 #define NDCR 0x00
521 reg = readl_relaxed(nfc->regs + NDCR);
522 writel_relaxed(reg | int_mask, nfc->regs + NDCR);
530 reg = readl_relaxed(nfc->regs + NDCR);
531 writel_relaxed(reg & ~int_mask, nfc->regs + NDCR);
559 ndcr = readl_relaxed(nfc->regs + NDCR);
566 writel_relaxed(ndcr, nfc->regs + NDCR);
579 ret = readl_relaxed_poll_timeout(nfc->regs + NDCR, val,
584 writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN,
585 nfc->regs + NDCR);
620 ndcr = readl_relaxed(nfc->regs + NDCR);
624 writel_relaxed(ndcr | NDCR_ND_RUN, nfc->regs + NDCR);
647 (u32)readl_relaxed(nfc->regs + NDCR), nfc_op->ndcb[0],
689 if (nfc->use_dma && (readl_relaxed(nfc->regs + NDCR) & NDCR_DMA_EN))
771 * Reset the NDCR register to a clean state for this particular chip,
774 ndcr_generic = readl_relaxed(nfc->regs + NDCR) &
776 writel_relaxed(ndcr_generic | marvell_nand->ndcr, nfc->regs + NDCR);
795 u32 ien = (~readl_relaxed(nfc->regs + NDCR)) & NDCR_ALL_INT;
798 * RDY interrupt mask is one bit in NDCR while there are two status
819 u32 ndcr = readl_relaxed(nfc->regs + NDCR);
822 writel_relaxed(ndcr | NDCR_ECC_EN, nfc->regs + NDCR);
836 u32 ndcr = readl_relaxed(nfc->regs + NDCR);
839 writel_relaxed(ndcr & ~NDCR_ECC_EN, nfc->regs + NDCR);
850 reg = readl_relaxed(nfc->regs + NDCR);
851 writel_relaxed(reg | NDCR_DMA_EN, nfc->regs + NDCR);
858 reg = readl_relaxed(nfc->regs + NDCR);
859 writel_relaxed(reg & ~NDCR_DMA_EN, nfc->regs + NDCR);
1880 * NDCR ND_RUN bit should be cleared automatically at the end of each
1887 writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN,
1888 nfc->regs + NDCR);
1952 * NDCR ND_RUN bit should be cleared automatically at the end of each
1959 writel_relaxed(readl(nfc->regs + NDCR) & ~NDCR_ND_RUN,
1960 nfc->regs + NDCR);
2514 /* Save the chip-specific fields of NDCR */
2894 NDCR_RD_ID_CNT(NFCV1_READID_LEN), nfc->regs + NDCR);