Lines Matching defs:page
25 * there are at most 2 bitflips. Here is the page layout used by the
35 * not align with the page (data + OOB) size. ECC bytes are always
36 * 30B per ECC chunk. Here is the page layout used by the controller
240 * @writesize: Full page size on which the layout applies
964 * check if the entire page (with ECC bytes) is actually blank or not.
1036 bool raw, int page)
1047 .ndcb[1] = NDCB1_ADDRS_PAGE(page),
1048 .ndcb[2] = NDCB2_ADDR5_PAGE(page),
1068 * Read the page then the OOB area. Unlike what is shown in current
1088 int oob_required, int page)
1092 true, page);
1096 int oob_required, int page)
1106 page);
1114 * When ECC failures are detected, check if the full page has been
1122 lt->data_bytes, true, page);
1135 static int marvell_nfc_hw_ecc_hmg_read_oob_raw(struct nand_chip *chip, int page)
1141 true, page);
1148 int page)
1161 .ndcb[1] = NDCB1_ADDRS_PAGE(page),
1162 .ndcb[2] = NDCB2_ADDR5_PAGE(page),
1182 /* Write the page then the OOB area */
1215 int oob_required, int page)
1219 true, page);
1224 int oob_required, int page)
1231 false, page);
1243 int page)
1252 true, page);
1257 int oob_required, int page)
1275 nand_read_page_op(chip, page, 0, NULL, 0);
1306 int page)
1316 .ndcb[1] = NDCB1_ADDRS_PAGE(page),
1317 .ndcb[2] = NDCB2_ADDR5_PAGE(page),
1372 int page)
1403 spare, spare_len, page);
1422 * user should re-read the page in raw mode if ECC bytes are required.
1427 * bytes in raw mode and check if the whole page is empty. In this case,
1431 * 2k page, 8b strength per 512B chunk), the controller tries to correct
1433 * this strange behavior, the whole page is re-read in raw mode, not
1471 * case, re-read the entire page.
1496 static int marvell_nfc_hw_ecc_bch_read_oob_raw(struct nand_chip *chip, int page)
1500 return chip->ecc.read_page_raw(chip, buf, true, page);
1503 static int marvell_nfc_hw_ecc_bch_read_oob(struct nand_chip *chip, int page)
1507 return chip->ecc.read_page(chip, buf, true, page);
1513 int oob_required, int page)
1527 nand_prog_page_begin_op(chip, page, 0, NULL, 0);
1568 int page)
1597 nfc_op.ndcb[1] |= NDCB1_ADDRS_PAGE(page);
1598 nfc_op.ndcb[2] |= NDCB2_ADDR5_PAGE(page);
1628 int oob_required, int page)
1656 spare, spare_len, page);
1688 int page)
1695 return chip->ecc.write_page_raw(chip, buf, true, page);
1698 static int marvell_nfc_hw_ecc_bch_write_oob(struct nand_chip *chip, int page)
1705 return chip->ecc.write_page(chip, buf, true, page);
2226 * 4KB page / 4bit BCH combination.
2273 "ECC strength %d at page size %d is not supported\n",
2520 * On small page NANDs, only one cycle is needed to pass the
2891 * offset in the read page and this will fail the protection.