Lines Matching defs:host
236 static void lpc32xx_nand_setup(struct lpc32xx_nand_host *host)
241 writel(SLCCTRL_SW_RESET, SLC_CTRL(host->io_base));
245 writel(0, SLC_CFG(host->io_base));
246 writel(0, SLC_IEN(host->io_base));
248 SLC_ICR(host->io_base));
251 clkrate = clk_get_rate(host->clk);
256 tmp = SLCTAC_WDR(host->ncfg->wdr_clks) |
257 SLCTAC_WWIDTH(clkrate, host->ncfg->wwidth) |
258 SLCTAC_WHOLD(clkrate, host->ncfg->whold) |
259 SLCTAC_WSETUP(clkrate, host->ncfg->wsetup) |
260 SLCTAC_RDR(host->ncfg->rdr_clks) |
261 SLCTAC_RWIDTH(clkrate, host->ncfg->rwidth) |
262 SLCTAC_RHOLD(clkrate, host->ncfg->rhold) |
263 SLCTAC_RSETUP(clkrate, host->ncfg->rsetup);
264 writel(tmp, SLC_TAC(host->io_base));
274 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
277 tmp = readl(SLC_CFG(host->io_base));
282 writel(tmp, SLC_CFG(host->io_base));
286 writel(cmd, SLC_CMD(host->io_base));
288 writel(cmd, SLC_ADDR(host->io_base));
297 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
300 if ((readl(SLC_STAT(host->io_base)) & SLCSTAT_NAND_READY) != 0)
309 static void lpc32xx_wp_enable(struct lpc32xx_nand_host *host)
311 if (host->wp_gpio)
312 gpiod_set_value_cansleep(host->wp_gpio, 1);
318 static void lpc32xx_wp_disable(struct lpc32xx_nand_host *host)
320 if (host->wp_gpio)
321 gpiod_set_value_cansleep(host->wp_gpio, 0);
351 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
353 return (uint8_t)readl(SLC_DATA(host->io_base));
361 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
365 *buf++ = (uint8_t)readl(SLC_DATA(host->io_base));
374 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
378 writel((uint32_t)*buf++, SLC_DATA(host->io_base));
429 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
434 host->dma_slave_config.direction = dir;
435 host->dma_slave_config.src_addr = dma;
436 host->dma_slave_config.dst_addr = dma;
437 host->dma_slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
438 host->dma_slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
439 host->dma_slave_config.src_maxburst = 4;
440 host->dma_slave_config.dst_maxburst = 4;
442 host->dma_slave_config.device_fc = false;
443 if (dmaengine_slave_config(host->dma_chan, &host->dma_slave_config)) {
448 sg_init_one(&host->sgl, mem, len);
450 res = dma_map_sg(host->dma_chan->device->dev, &host->sgl, 1,
456 desc = dmaengine_prep_slave_sg(host->dma_chan, &host->sgl, 1, dir,
463 init_completion(&host->comp);
465 desc->callback_param = &host->comp;
468 dma_async_issue_pending(host->dma_chan);
470 wait_for_completion_timeout(&host->comp, msecs_to_jiffies(1000));
472 dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
477 dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
489 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
502 dma_buf = host->data_buf;
505 memcpy(host->data_buf, buf, mtd->writesize);
509 writel(readl(SLC_CFG(host->io_base)) |
511 SLCCFG_DMA_BURST, SLC_CFG(host->io_base));
513 writel((readl(SLC_CFG(host->io_base)) |
516 SLC_CFG(host->io_base));
520 writel(SLCCTRL_ECC_CLEAR, SLC_CTRL(host->io_base));
523 writel(mtd->writesize, SLC_TC(host->io_base));
526 writel(readl(SLC_CTRL(host->io_base)) | SLCCTRL_DMA_START,
527 SLC_CTRL(host->io_base));
531 res = lpc32xx_xmit_dma(mtd, SLC_DMA_DATA(host->io_base_dma),
542 res = lpc32xx_xmit_dma(mtd, SLC_ECC(host->io_base_dma),
543 &host->ecc_buf[i], 4, DMA_DEV_TO_MEM);
555 if (readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO) {
558 while ((readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO) &&
570 host->ecc_buf[chip->ecc.steps - 1] =
571 readl(SLC_ECC(host->io_base));
574 dmaengine_terminate_all(host->dma_chan);
576 if (readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO ||
577 readl(SLC_TC(host->io_base))) {
584 writel(readl(SLC_CTRL(host->io_base)) & ~SLCCTRL_DMA_START,
585 SLC_CTRL(host->io_base));
586 writel(readl(SLC_CFG(host->io_base)) &
588 SLCCFG_DMA_BURST), SLC_CFG(host->io_base));
591 memcpy(buf, host->data_buf, mtd->writesize);
604 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
619 lpc32xx_slc_ecc_copy(tmpecc, (uint32_t *) host->ecc_buf, chip->ecc.steps);
672 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
693 lpc32xx_slc_ecc_copy(pb, (uint32_t *)host->ecc_buf, chip->ecc.steps);
719 static int lpc32xx_nand_dma_setup(struct lpc32xx_nand_host *host)
721 struct mtd_info *mtd = nand_to_mtd(&host->nand_chip);
724 if (!host->pdata || !host->pdata->dma_filter) {
731 host->dma_chan = dma_request_channel(mask, host->pdata->dma_filter,
733 if (!host->dma_chan) {
772 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
778 host->ecc_buf = (uint32_t *)(host->data_buf + LPC32XX_DMA_DATA_SIZE);
828 struct lpc32xx_nand_host *host;
835 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
836 if (!host)
839 host->io_base = devm_platform_get_and_ioremap_resource(pdev, 0, &rc);
840 if (IS_ERR(host->io_base))
841 return PTR_ERR(host->io_base);
843 host->io_base_dma = rc->start;
845 host->ncfg = lpc32xx_parse_dt(&pdev->dev);
846 if (!host->ncfg) {
853 host->wp_gpio = gpiod_get_optional(&pdev->dev, NULL, GPIOD_OUT_LOW);
854 res = PTR_ERR_OR_ZERO(host->wp_gpio);
862 gpiod_set_consumer_name(host->wp_gpio, "NAND WP");
864 host->pdata = dev_get_platdata(&pdev->dev);
866 chip = &host->nand_chip;
868 nand_set_controller_data(chip, host);
874 host->clk = devm_clk_get_enabled(&pdev->dev, NULL);
875 if (IS_ERR(host->clk)) {
882 chip->legacy.IO_ADDR_R = SLC_DATA(host->io_base);
883 chip->legacy.IO_ADDR_W = SLC_DATA(host->io_base);
889 lpc32xx_nand_setup(host);
891 platform_set_drvdata(pdev, host);
902 host->dma_buf_len = LPC32XX_DMA_DATA_SIZE + LPC32XX_ECC_SAVE_SIZE;
903 host->data_buf = devm_kzalloc(&pdev->dev, host->dma_buf_len,
905 if (host->data_buf == NULL) {
910 res = lpc32xx_nand_dma_setup(host);
923 res = mtd_device_register(mtd, host->ncfg->parts,
924 host->ncfg->num_parts);
933 dma_release_channel(host->dma_chan);
935 lpc32xx_wp_enable(host);
946 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
947 struct nand_chip *chip = &host->nand_chip;
953 dma_release_channel(host->dma_chan);
956 tmp = readl(SLC_CTRL(host->io_base));
958 writel(tmp, SLC_CTRL(host->io_base));
960 lpc32xx_wp_enable(host);
965 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
969 ret = clk_prepare_enable(host->clk);
974 lpc32xx_nand_setup(host);
977 lpc32xx_wp_disable(host);
985 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
988 tmp = readl(SLC_CTRL(host->io_base));
990 writel(tmp, SLC_CTRL(host->io_base));
993 lpc32xx_wp_enable(host);
996 clk_disable_unprepare(host->clk);