Lines Matching defs:host
144 static inline unsigned int hinfc_read(struct hinfc_host *host, unsigned int reg)
146 return readl(host->iobase + reg);
149 static inline void hinfc_write(struct hinfc_host *host, unsigned int value,
152 writel(value, host->iobase + reg);
155 static void wait_controller_finished(struct hinfc_host *host)
161 val = hinfc_read(host, HINFC504_STATUS);
162 if (host->command == NAND_CMD_ERASE2) {
166 val = hinfc_read(host, HINFC504_STATUS);
176 dev_err(host->dev, "Wait NAND controller exec cmd timeout.\n");
179 static void hisi_nfc_dma_transfer(struct hinfc_host *host, int todev)
181 struct nand_chip *chip = &host->chip;
186 hinfc_write(host, host->dma_buffer, HINFC504_DMA_ADDR_DATA);
187 hinfc_write(host, host->dma_oob, HINFC504_DMA_ADDR_OOB);
190 hinfc_write(host, ((mtd->oobsize & HINFC504_DMA_LEN_OOB_MASK)
193 hinfc_write(host, HINFC504_DMA_PARA_DATA_RW_EN
196 if (host->command == NAND_CMD_READOOB)
197 hinfc_write(host, HINFC504_DMA_PARA_OOB_RW_EN
201 hinfc_write(host, HINFC504_DMA_PARA_DATA_RW_EN
213 | ((host->addr_cycle == 4 ? 1 : 0)
215 | ((host->chipselect & HINFC504_DMA_CTRL_CS_MASK)
221 init_completion(&host->cmd_complete);
223 hinfc_write(host, val, HINFC504_DMA_CTRL);
224 ret = wait_for_completion_timeout(&host->cmd_complete,
228 dev_err(host->dev, "DMA operation(irq) timeout!\n");
230 val = hinfc_read(host, HINFC504_DMA_CTRL);
232 dev_err(host->dev, "DMA is already done but without irq ACK!\n");
234 dev_err(host->dev, "DMA is really timeout!\n");
238 static int hisi_nfc_send_cmd_pageprog(struct hinfc_host *host)
240 host->addr_value[0] &= 0xffff0000;
242 hinfc_write(host, host->addr_value[0], HINFC504_ADDRL);
243 hinfc_write(host, host->addr_value[1], HINFC504_ADDRH);
244 hinfc_write(host, NAND_CMD_PAGEPROG << 8 | NAND_CMD_SEQIN,
247 hisi_nfc_dma_transfer(host, 1);
252 static int hisi_nfc_send_cmd_readstart(struct hinfc_host *host)
254 struct mtd_info *mtd = nand_to_mtd(&host->chip);
256 if ((host->addr_value[0] == host->cache_addr_value[0]) &&
257 (host->addr_value[1] == host->cache_addr_value[1]))
260 host->addr_value[0] &= 0xffff0000;
262 hinfc_write(host, host->addr_value[0], HINFC504_ADDRL);
263 hinfc_write(host, host->addr_value[1], HINFC504_ADDRH);
264 hinfc_write(host, NAND_CMD_READSTART << 8 | NAND_CMD_READ0,
267 hinfc_write(host, 0, HINFC504_LOG_READ_ADDR);
268 hinfc_write(host, mtd->writesize + mtd->oobsize,
271 hisi_nfc_dma_transfer(host, 0);
273 host->cache_addr_value[0] = host->addr_value[0];
274 host->cache_addr_value[1] = host->addr_value[1];
279 static int hisi_nfc_send_cmd_erase(struct hinfc_host *host)
281 hinfc_write(host, host->addr_value[0], HINFC504_ADDRL);
282 hinfc_write(host, (NAND_CMD_ERASE2 << 8) | NAND_CMD_ERASE1,
285 hinfc_write(host, HINFC504_OP_WAIT_READY_EN
289 | ((host->chipselect & HINFC504_OP_NF_CS_MASK)
291 | ((host->addr_cycle & HINFC504_OP_ADDR_CYCLE_MASK)
295 wait_controller_finished(host);
300 static int hisi_nfc_send_cmd_readid(struct hinfc_host *host)
302 hinfc_write(host, HINFC504_NANDINFO_LEN, HINFC504_DATA_NUM);
303 hinfc_write(host, NAND_CMD_READID, HINFC504_CMD);
304 hinfc_write(host, 0, HINFC504_ADDRL);
306 hinfc_write(host, HINFC504_OP_CMD1_EN | HINFC504_OP_ADDR_EN
308 | ((host->chipselect & HINFC504_OP_NF_CS_MASK)
312 wait_controller_finished(host);
317 static int hisi_nfc_send_cmd_status(struct hinfc_host *host)
319 hinfc_write(host, HINFC504_NANDINFO_LEN, HINFC504_DATA_NUM);
320 hinfc_write(host, NAND_CMD_STATUS, HINFC504_CMD);
321 hinfc_write(host, HINFC504_OP_CMD1_EN
323 | ((host->chipselect & HINFC504_OP_NF_CS_MASK)
327 wait_controller_finished(host);
332 static int hisi_nfc_send_cmd_reset(struct hinfc_host *host, int chipselect)
334 hinfc_write(host, NAND_CMD_RESET, HINFC504_CMD);
336 hinfc_write(host, HINFC504_OP_CMD1_EN
342 wait_controller_finished(host);
349 struct hinfc_host *host = nand_get_controller_data(chip);
354 host->chipselect = chipselect;
359 struct hinfc_host *host = nand_get_controller_data(chip);
361 if (host->command == NAND_CMD_STATUS)
362 return *(uint8_t *)(host->mmio);
364 host->offset++;
366 if (host->command == NAND_CMD_READID)
367 return *(uint8_t *)(host->mmio + host->offset - 1);
369 return *(uint8_t *)(host->buffer + host->offset - 1);
375 struct hinfc_host *host = nand_get_controller_data(chip);
377 memcpy(host->buffer + host->offset, buf, len);
378 host->offset += len;
383 struct hinfc_host *host = nand_get_controller_data(chip);
385 memcpy(buf, host->buffer + host->offset, len);
386 host->offset += len;
392 struct hinfc_host *host = nand_get_controller_data(chip);
393 unsigned int command = host->command;
395 host->addr_cycle = 0;
396 host->addr_value[0] = 0;
397 host->addr_value[1] = 0;
406 host->addr_value[0] = column & 0xffff;
407 host->addr_cycle = 2;
410 host->addr_value[0] |= (page_addr & 0xffff)
411 << (host->addr_cycle * 8);
412 host->addr_cycle += 2;
414 host->addr_cycle += 1;
415 if (host->command == NAND_CMD_ERASE1)
416 host->addr_value[0] |= ((page_addr >> 16) & 0xff) << 16;
418 host->addr_value[1] |= ((page_addr >> 16) & 0xff);
427 struct hinfc_host *host = nand_get_controller_data(chip);
431 host->command = command;
437 host->offset = column;
439 host->offset = column + mtd->writesize;
443 hisi_nfc_send_cmd_readstart(host);
447 host->offset = column;
456 hisi_nfc_send_cmd_pageprog(host);
460 hisi_nfc_send_cmd_erase(host);
464 host->offset = column;
465 memset(host->mmio, 0, 0x10);
466 hisi_nfc_send_cmd_readid(host);
470 flag = hinfc_read(host, HINFC504_CON);
472 hinfc_write(host,
476 host->offset = 0;
477 memset(host->mmio, 0, 0x10);
478 hisi_nfc_send_cmd_status(host);
479 hinfc_write(host, flag, HINFC504_CON);
483 hisi_nfc_send_cmd_reset(host, host->chipselect);
487 dev_err(host->dev, "Error: unsupported cmd(cmd=%x, col=%x, page=%x)\n",
492 host->cache_addr_value[0] = ~0;
493 host->cache_addr_value[1] = ~0;
499 struct hinfc_host *host = devid;
502 flag = hinfc_read(host, HINFC504_INTS);
504 host->irq_status |= flag;
507 hinfc_write(host, HINFC504_INTCLR_DMA, HINFC504_INTCLR);
508 complete(&host->cmd_complete);
510 hinfc_write(host, HINFC504_INTCLR_CE, HINFC504_INTCLR);
512 hinfc_write(host, HINFC504_INTCLR_UE, HINFC504_INTCLR);
522 struct hinfc_host *host = nand_get_controller_data(chip);
530 if (host->irq_status & HINFC504_INTS_UE) {
532 } else if (host->irq_status & HINFC504_INTS_CE) {
536 status_ecc = hinfc_read(host, HINFC504_ECC_STATUS) >>
546 host->irq_status = 0;
554 struct hinfc_host *host = nand_get_controller_data(chip);
558 if (host->irq_status & HINFC504_INTS_UE) {
559 host->irq_status = 0;
563 host->irq_status = 0;
580 static void hisi_nfc_host_init(struct hinfc_host *host)
582 struct nand_chip *chip = &host->chip;
585 host->version = hinfc_read(host, HINFC_VERSION);
586 host->addr_cycle = 0;
587 host->addr_value[0] = 0;
588 host->addr_value[1] = 0;
589 host->cache_addr_value[0] = ~0;
590 host->cache_addr_value[1] = ~0;
591 host->chipselect = 0;
601 hinfc_write(host, flag, HINFC504_CON);
603 memset(host->mmio, 0xff, HINFC504_BUFFER_BASE_ADDRESS_LEN);
605 hinfc_write(host, SET_HINFC504_PWIDTH(HINFC504_W_LATCH,
609 hinfc_write(host, HINFC504_INTEN_DMA, HINFC504_INTEN);
636 static int hisi_nfc_ecc_probe(struct hinfc_host *host)
640 struct device *dev = host->dev;
641 struct nand_chip *chip = &host->chip;
679 flag = hinfc_read(host, HINFC504_CON);
683 hinfc_write(host, flag, HINFC504_CON);
686 flag = hinfc_read(host, HINFC504_INTEN) & 0xfff;
687 hinfc_write(host, flag | HINFC504_INTEN_UE | HINFC504_INTEN_CE,
696 struct hinfc_host *host = nand_get_controller_data(chip);
699 host->buffer = dmam_alloc_coherent(host->dev,
701 &host->dma_buffer, GFP_KERNEL);
702 if (!host->buffer)
705 host->dma_oob = host->dma_buffer + mtd->writesize;
706 memset(host->buffer, 0xff, mtd->writesize + mtd->oobsize);
708 flag = hinfc_read(host, HINFC504_CON);
719 dev_err(host->dev, "NON-2KB page size nand flash\n");
722 hinfc_write(host, flag, HINFC504_CON);
725 hisi_nfc_ecc_probe(host);
738 struct hinfc_host *host;
743 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
744 if (!host)
746 host->dev = dev;
748 platform_set_drvdata(pdev, host);
749 chip = &host->chip;
756 host->iobase = devm_platform_ioremap_resource(pdev, 0);
757 if (IS_ERR(host->iobase))
758 return PTR_ERR(host->iobase);
760 host->mmio = devm_platform_ioremap_resource(pdev, 1);
761 if (IS_ERR(host->mmio))
762 return PTR_ERR(host->mmio);
767 nand_set_controller_data(chip, host);
778 hisi_nfc_host_init(host);
780 ret = devm_request_irq(dev, irq, hinfc_irq_handle, 0x0, "nandc", host);
803 struct hinfc_host *host = platform_get_drvdata(pdev);
804 struct nand_chip *chip = &host->chip;
815 struct hinfc_host *host = dev_get_drvdata(dev);
819 if (((hinfc_read(host, HINFC504_STATUS) & 0x1) == 0x0) &&
820 (hinfc_read(host, HINFC504_DMA_CTRL) &
827 dev_err(host->dev, "nand controller suspend timeout.\n");
835 struct hinfc_host *host = dev_get_drvdata(dev);
836 struct nand_chip *chip = &host->chip;
839 hisi_nfc_send_cmd_reset(host, cs);
840 hinfc_write(host, SET_HINFC504_PWIDTH(HINFC504_W_LATCH,