Lines Matching refs:cafe
101 #define cafe_readl(cafe, addr) readl((cafe)->mmio + CAFE_##addr)
102 #define cafe_writel(cafe, datum, addr) writel(datum, (cafe)->mmio + CAFE_##addr)
106 struct cafe_priv *cafe = nand_get_controller_data(chip);
107 int result = !!(cafe_readl(cafe, NAND_STATUS) & 0x40000000);
108 uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
110 cafe_writel(cafe, irqs, NAND_IRQ);
112 cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n",
113 result?"":" not", irqs, cafe_readl(cafe, NAND_IRQ),
114 cafe_readl(cafe, GLOBAL_IRQ), cafe_readl(cafe, GLOBAL_IRQ_MASK));
122 struct cafe_priv *cafe = nand_get_controller_data(chip);
124 if (cafe->usedma)
125 memcpy(cafe->dmabuf + cafe->datalen, buf, len);
127 memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len);
129 cafe->datalen += len;
131 cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes to write buffer. datalen 0x%x\n",
132 len, cafe->datalen);
137 struct cafe_priv *cafe = nand_get_controller_data(chip);
139 if (cafe->usedma)
140 memcpy(buf, cafe->dmabuf + cafe->datalen, len);
142 memcpy_fromio(buf, cafe->mmio + CAFE_NAND_READ_DATA + cafe->datalen, len);
144 cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes from position 0x%x in read buffer.\n",
145 len, cafe->datalen);
146 cafe->datalen += len;
151 struct cafe_priv *cafe = nand_get_controller_data(chip);
155 cafe_dev_dbg(&cafe->pdev->dev, "Read %02x\n", d);
164 struct cafe_priv *cafe = nand_get_controller_data(chip);
169 cafe_dev_dbg(&cafe->pdev->dev, "cmdfunc %02x, 0x%x, 0x%x\n",
174 cafe_writel(cafe, cafe->ctl2 | 0x100 | command, NAND_CTRL2);
175 ctl1 = cafe->ctl1;
176 cafe->ctl2 &= ~(1<<30);
177 cafe_dev_dbg(&cafe->pdev->dev, "Continue command, ctl1 %08x, #data %d\n",
178 cafe->ctl1, cafe->nr_data);
182 cafe_writel(cafe, 0, NAND_CTRL2);
195 cafe_writel(cafe, column, NAND_ADDR1);
200 cafe_writel(cafe, page_addr & 0xffff, NAND_ADDR1);
203 cafe_writel(cafe, page_addr, NAND_ADDR2);
209 cafe->data_pos = cafe->datalen = 0;
212 ctl1 = 0x80000000 | command | (cafe->ctl1 & CTRL1_CHIPSELECT);
218 cafe->datalen = 4;
225 cafe->datalen = mtd->writesize + mtd->oobsize - column;
236 cafe->ctl1 = ctl1;
237 cafe_dev_dbg(&cafe->pdev->dev, "Setup for delayed command, ctl1 %08x, dlen %x\n",
238 cafe->ctl1, cafe->datalen);
243 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, NAND_CTRL2);
245 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_READSTART, NAND_CTRL2);
248 cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n",
249 cafe->datalen, ctl1, cafe_readl(cafe, NAND_CTRL2));
252 cafe_writel(cafe, cafe->datalen, NAND_DATA_LEN);
253 cafe_writel(cafe, 0x90000000, NAND_IRQ);
254 if (cafe->usedma && (ctl1 & (3<<25))) {
255 uint32_t dmactl = 0xc0000000 + cafe->datalen;
264 cafe_writel(cafe, dmactl, NAND_DMA_CTRL);
266 cafe->datalen = 0;
272 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
275 cafe_writel(cafe, ctl1, NAND_CTRL1);
285 irqs = cafe_readl(cafe, NAND_IRQ);
290 cafe_dev_dbg(&cafe->pdev->dev, "Wait for ready, IRQ %x\n", irqs);
293 cafe_writel(cafe, doneint, NAND_IRQ);
294 cafe_dev_dbg(&cafe->pdev->dev, "Command %x completed after %d usec, irqs %x (%x)\n",
295 command, 500000-c, irqs, cafe_readl(cafe, NAND_IRQ));
298 WARN_ON(cafe->ctl2 & (1<<30));
310 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
314 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
319 struct cafe_priv *cafe = nand_get_controller_data(chip);
321 cafe_dev_dbg(&cafe->pdev->dev, "select_chip %d\n", chipnr);
326 cafe->ctl1 |= CTRL1_CHIPSELECT;
328 cafe->ctl1 &= ~CTRL1_CHIPSELECT;
335 struct cafe_priv *cafe = nand_get_controller_data(chip);
336 uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
337 cafe_writel(cafe, irqs & ~0x90000000, NAND_IRQ);
341 cafe_dev_dbg(&cafe->pdev->dev, "irq, bits %x (%x)\n", irqs, cafe_readl(cafe, NAND_IRQ));
374 struct cafe_priv *cafe = nand_get_controller_data(chip);
377 cafe_dev_dbg(&cafe->pdev->dev, "ECC result %08x SYN1,2 %08x\n",
378 cafe_readl(cafe, NAND_ECC_RESULT),
379 cafe_readl(cafe, NAND_ECC_SYN01));
384 if (checkecc && cafe_readl(cafe, NAND_ECC_RESULT) & (1<<18)) {
391 uint32_t tmp = cafe_readl(cafe, NAND_ECC_SYN01 + (i*2));
393 syn[i] = cafe->rs->codec->index_of[tmp & 0xfff];
394 syn[i+1] = cafe->rs->codec->index_of[(tmp >> 16) & 0xfff];
397 n = decode_rs16(cafe->rs, NULL, NULL, 1367, syn, 0, pos, 0,
435 dev_dbg(&cafe->pdev->dev, "Failed to correct ECC at %08x\n",
436 cafe_readl(cafe, NAND_ADDR2) * 2048);
438 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
441 dev_dbg(&cafe->pdev->dev, "Corrected %d symbol errors\n", n);
538 struct cafe_priv *cafe = nand_get_controller_data(chip);
544 cafe->ctl2 |= (1<<30);
594 struct cafe_priv *cafe = nand_get_controller_data(chip);
597 cafe->dmabuf = dma_alloc_coherent(&cafe->pdev->dev, 2112,
598 &cafe->dmaaddr, GFP_KERNEL);
599 if (!cafe->dmabuf)
603 cafe_writel(cafe, lower_32_bits(cafe->dmaaddr), NAND_DMA_ADDR0);
604 cafe_writel(cafe, upper_32_bits(cafe->dmaaddr), NAND_DMA_ADDR1);
606 cafe_dev_dbg(&cafe->pdev->dev, "Set DMA address to %x (virt %p)\n",
607 cafe_readl(cafe, NAND_DMA_ADDR0), cafe->dmabuf);
610 cafe->usedma = usedma;
612 cafe->ctl2 = BIT(27); /* Reed-Solomon ECC */
614 cafe->ctl2 |= BIT(29); /* 2KiB page size */
619 cafe->nand.bbt_td = &cafe_bbt_main_descr_2048;
620 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_2048;
622 cafe->nand.bbt_td = &cafe_bbt_main_descr_512;
623 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_512;
625 dev_warn(&cafe->pdev->dev,
632 cafe->nand.ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
633 cafe->nand.ecc.placement = NAND_ECC_PLACEMENT_INTERLEAVED;
634 cafe->nand.ecc.size = mtd->writesize;
635 cafe->nand.ecc.bytes = 14;
636 cafe->nand.ecc.strength = 4;
637 cafe->nand.ecc.write_page = cafe_nand_write_page_lowlevel;
638 cafe->nand.ecc.write_oob = cafe_nand_write_oob;
639 cafe->nand.ecc.read_page = cafe_nand_read_page;
640 cafe->nand.ecc.read_oob = cafe_nand_read_oob;
645 dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
652 struct cafe_priv *cafe = nand_get_controller_data(chip);
654 dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
666 struct cafe_priv *cafe;
681 cafe = kzalloc(sizeof(*cafe), GFP_KERNEL);
682 if (!cafe) {
687 mtd = nand_to_mtd(&cafe->nand);
689 nand_set_controller_data(&cafe->nand, cafe);
691 cafe->pdev = pdev;
692 cafe->mmio = pci_iomap(pdev, 0, 0);
693 if (!cafe->mmio) {
699 cafe->rs = init_rs_non_canonical(12, &cafe_mul, 0, 1, 8);
700 if (!cafe->rs) {
705 cafe->nand.legacy.cmdfunc = cafe_nand_cmdfunc;
706 cafe->nand.legacy.dev_ready = cafe_device_ready;
707 cafe->nand.legacy.read_byte = cafe_read_byte;
708 cafe->nand.legacy.read_buf = cafe_read_buf;
709 cafe->nand.legacy.write_buf = cafe_write_buf;
710 cafe->nand.legacy.select_chip = cafe_select_chip;
711 cafe->nand.legacy.set_features = nand_get_set_features_notsupp;
712 cafe->nand.legacy.get_features = nand_get_set_features_notsupp;
714 cafe->nand.legacy.chip_delay = 0;
717 cafe->nand.bbt_options = NAND_BBT_USE_FLASH;
720 cafe->nand.options |= NAND_SKIP_BBTSCAN | NAND_NO_BBM_QUIRK;
723 dev_warn(&cafe->pdev->dev, "%d timing register values ignored; precisely three are required\n", numtimings);
727 cafe_dev_dbg(&cafe->pdev->dev, "Using provided timings (%08x %08x %08x)\n",
730 timing[0] = cafe_readl(cafe, NAND_TIMING1);
731 timing[1] = cafe_readl(cafe, NAND_TIMING2);
732 timing[2] = cafe_readl(cafe, NAND_TIMING3);
735 cafe_dev_dbg(&cafe->pdev->dev, "Timing registers already set (%08x %08x %08x)\n",
738 dev_warn(&cafe->pdev->dev, "Timing registers unset; using most conservative defaults\n");
744 cafe_writel(cafe, 1, NAND_RESET);
745 cafe_writel(cafe, 0, NAND_RESET);
747 cafe_writel(cafe, timing[0], NAND_TIMING1);
748 cafe_writel(cafe, timing[1], NAND_TIMING2);
749 cafe_writel(cafe, timing[2], NAND_TIMING3);
751 cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
760 ctrl = cafe_readl(cafe, GLOBAL_CTRL);
763 cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
764 cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
765 cafe_writel(cafe, 0, NAND_DMA_CTRL);
767 cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
768 cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
771 cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
772 cafe_dev_dbg(&cafe->pdev->dev, "Control %x, IRQ mask %x\n",
773 cafe_readl(cafe, GLOBAL_CTRL),
774 cafe_readl(cafe, GLOBAL_IRQ_MASK));
777 cafe->usedma = 0;
780 cafe->nand.legacy.dummy_controller.ops = &cafe_nand_controller_ops;
781 err = nand_scan(&cafe->nand, 2);
795 nand_cleanup(&cafe->nand);
798 cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
801 free_rs(cafe->rs);
803 pci_iounmap(pdev, cafe->mmio);
805 kfree(cafe);
816 struct cafe_priv *cafe = nand_get_controller_data(chip);
820 cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
825 free_rs(cafe->rs);
826 pci_iounmap(pdev, cafe->mmio);
827 dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
828 kfree(cafe);
845 struct cafe_priv *cafe = nand_get_controller_data(chip);
848 cafe_writel(cafe, 1, NAND_RESET);
849 cafe_writel(cafe, 0, NAND_RESET);
850 cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
853 cafe_writel(cafe, timing[0], NAND_TIMING1);
854 cafe_writel(cafe, timing[1], NAND_TIMING2);
855 cafe_writel(cafe, timing[2], NAND_TIMING3);
858 ctrl = cafe_readl(cafe, GLOBAL_CTRL);
861 cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
862 cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
863 cafe_writel(cafe, 0, NAND_DMA_CTRL);
864 cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
865 cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
868 cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0);
869 if (sizeof(cafe->dmaaddr) > 4)
871 cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1);
873 cafe_writel(cafe, 0, NAND_DMA_ADDR1);
876 cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);