Lines Matching defs:timing
242 /* Register controlling DQ related timing. */
244 /* Register controlling DSQ related timing. */
250 /* Register controlling the gate and loopback control related timing. */
2317 static int calc_cycl(u32 timing, u32 clock)
2319 if (timing == 0 || clock == 0)
2322 if ((timing % clock) > 0)
2323 return timing / clock;
2325 return timing / clock - 1;
2394 * for SDR timing modes 1, 2, 3, 4 and 5.
2395 * If clk_period is 20ns the condition is met only for SDR timing
2521 * If timing exceeds delay field in timing register