Lines Matching defs:ecc
769 /* v7.2 has different ecc level shift in the acc register */
1242 .ecc = brcmnand_hamming_ooblayout_ecc,
1258 oobregion->offset = ((section + 1) * sas) - chip->ecc.bytes;
1259 oobregion->length = chip->ecc.bytes;
1276 if (sas <= chip->ecc.bytes)
1280 oobregion->length = sas - chip->ecc.bytes;
1298 if (section > 1 || sas - chip->ecc.bytes < 6 ||
1299 (section && sas - chip->ecc.bytes == 6))
1307 oobregion->length = sas - chip->ecc.bytes - 6;
1314 .ecc = brcmnand_bch_ooblayout_ecc,
1319 .ecc = brcmnand_bch_ooblayout_ecc,
1327 struct nand_ecc_ctrl *ecc = &host->chip.ecc;
1336 ecc->bytes = 3 * sectors;
1347 ecc->bytes = DIV_ROUND_UP(ecc_level * 14, 8);
1353 if (ecc->bytes >= sas) {
1356 ecc->bytes, sas);
2214 struct mtd_oob_region ecc;
2225 /* read without ecc for verification */
2226 ret = chip->ecc.read_page_raw(chip, buf, true, page);
2230 for (i = 0; i < chip->ecc.steps; i++) {
2231 ecc_chunk = buf + chip->ecc.size * i;
2233 mtd_ooblayout_ecc(mtd, i, &ecc);
2234 ecc_bytes = chip->oob_poi + ecc.offset;
2236 ret = nand_check_erased_ecc_chunk(ecc_chunk, chip->ecc.size,
2237 ecc_bytes, ecc.length,
2239 chip->ecc.strength);
2613 brcmnand_wr_corr_thresh(host, DIV_ROUND_UP(chip->ecc.strength * 3, 4));
2692 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) {
2694 chip->ecc.engine_type);
2698 if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) {
2699 if (chip->ecc.strength == 1 && chip->ecc.size == 512)
2701 chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
2704 chip->ecc.algo = NAND_ECC_ALGO_BCH;
2707 if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING &&
2708 (chip->ecc.strength != 1 || chip->ecc.size != 512)) {
2710 chip->ecc.strength, chip->ecc.size);
2714 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_NONE &&
2715 (!chip->ecc.size || !chip->ecc.strength)) {
2718 chip->ecc.size = requirements->step_size;
2719 chip->ecc.strength = requirements->strength;
2721 chip->ecc.size, chip->ecc.strength);
2725 switch (chip->ecc.size) {
2727 if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING)
2730 cfg->ecc_level = chip->ecc.strength;
2738 if (chip->ecc.strength & 0x1) {
2744 cfg->ecc_level = chip->ecc.strength >> 1;
2749 chip->ecc.size);
2806 chip->ecc.size = host->hwcfg.sector_size_1k ? 1024 : 512;
2815 chip->ecc.write_oob = brcmnand_write_oob_raw;
2816 chip->ecc.read_oob = brcmnand_read_oob_raw;
2855 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
2856 chip->ecc.read_page = brcmnand_read_page;
2857 chip->ecc.write_page = brcmnand_write_page;
2858 chip->ecc.read_page_raw = brcmnand_read_page_raw;
2859 chip->ecc.write_page_raw = brcmnand_write_page_raw;
2860 chip->ecc.write_oob_raw = brcmnand_write_oob_raw;
2861 chip->ecc.read_oob_raw = brcmnand_read_oob_raw;
2862 chip->ecc.read_oob = brcmnand_read_oob;
2863 chip->ecc.write_oob = brcmnand_write_oob;
3278 host->chip.ecc.size = pd->ecc_stepsize;
3279 host->chip.ecc.strength = pd->ecc_strength;