Lines Matching refs:nfc
234 static int anfc_wait_for_event(struct arasan_nfc *nfc, unsigned int event)
239 ret = readl_relaxed_poll_timeout(nfc->base + INTR_STS_REG, val,
243 dev_err(nfc->dev, "Timeout waiting for event 0x%x\n", event);
247 writel_relaxed(event, nfc->base + INTR_STS_REG);
252 static int anfc_wait_for_rb(struct arasan_nfc *nfc, struct nand_chip *chip,
260 ret = readl_relaxed_poll_timeout(nfc->base + READY_STS_REG, val,
264 dev_err(nfc->dev, "Timeout waiting for R/B 0x%x\n",
265 readl_relaxed(nfc->base + READY_STS_REG));
272 static void anfc_trigger_op(struct arasan_nfc *nfc, struct anfc_op *nfc_op)
274 writel_relaxed(nfc_op->pkt_reg, nfc->base + PKT_REG);
275 writel_relaxed(nfc_op->addr1_reg, nfc->base + MEM_ADDR1_REG);
276 writel_relaxed(nfc_op->addr2_reg, nfc->base + MEM_ADDR2_REG);
277 writel_relaxed(nfc_op->cmd_reg, nfc->base + CMD_REG);
278 writel_relaxed(nfc_op->prog_reg, nfc->base + PROG_REG);
304 static bool anfc_is_gpio_cs(struct arasan_nfc *nfc, int nfc_cs)
306 return nfc_cs >= 0 && nfc->cs_array[nfc_cs];
314 static void anfc_assert_cs(struct arasan_nfc *nfc, unsigned int nfc_cs_idx)
317 if (nfc->cur_cs == nfc_cs_idx)
321 if (anfc_is_gpio_cs(nfc, nfc->cur_cs))
322 gpiod_set_value_cansleep(nfc->cs_array[nfc->cur_cs], 1);
325 if (anfc_is_gpio_cs(nfc, nfc_cs_idx)) {
326 nfc->native_cs = nfc->spare_cs;
327 gpiod_set_value_cansleep(nfc->cs_array[nfc_cs_idx], 0);
329 nfc->native_cs = nfc_cs_idx;
332 nfc->cur_cs = nfc_cs_idx;
338 struct arasan_nfc *nfc = to_anfc(chip->controller);
342 anfc_assert_cs(nfc, nfc_cs_idx);
345 writel_relaxed(anand->data_iface, nfc->base + DATA_INTERFACE_REG);
346 writel_relaxed(anand->timings, nfc->base + TIMING_REG);
349 if (nfc->cur_clk != anand->clk) {
350 clk_disable_unprepare(nfc->bus_clk);
351 ret = clk_set_rate(nfc->bus_clk, anand->clk);
353 dev_err(nfc->dev, "Failed to change clock rate\n");
357 ret = clk_prepare_enable(nfc->bus_clk);
359 dev_err(nfc->dev,
364 nfc->cur_clk = anand->clk;
395 struct arasan_nfc *nfc = to_anfc(chip->controller);
412 ADDR2_CS(nfc->native_cs),
423 dma_addr = dma_map_single(nfc->dev, (void *)buf, len, DMA_FROM_DEVICE);
424 if (dma_mapping_error(nfc->dev, dma_addr)) {
425 dev_err(nfc->dev, "Buffer mapping error");
429 writel_relaxed(lower_32_bits(dma_addr), nfc->base + DMA_ADDR0_REG);
430 writel_relaxed(upper_32_bits(dma_addr), nfc->base + DMA_ADDR1_REG);
432 anfc_trigger_op(nfc, &nfc_op);
434 ret = anfc_wait_for_event(nfc, XFER_COMPLETE);
435 dma_unmap_single(nfc->dev, dma_addr, len, DMA_FROM_DEVICE);
437 dev_err(nfc->dev, "Error reading page %d\n", page);
514 struct arasan_nfc *nfc = to_anfc(chip->controller);
530 ADDR2_CS(nfc->native_cs),
542 writel_relaxed(anand->ecc_conf, nfc->base + ECC_CONF_REG);
545 nfc->base + ECC_SP_REG);
547 dma_addr = dma_map_single(nfc->dev, (void *)buf, len, DMA_TO_DEVICE);
548 if (dma_mapping_error(nfc->dev, dma_addr)) {
549 dev_err(nfc->dev, "Buffer mapping error");
553 writel_relaxed(lower_32_bits(dma_addr), nfc->base + DMA_ADDR0_REG);
554 writel_relaxed(upper_32_bits(dma_addr), nfc->base + DMA_ADDR1_REG);
556 anfc_trigger_op(nfc, &nfc_op);
557 ret = anfc_wait_for_event(nfc, XFER_COMPLETE);
558 dma_unmap_single(nfc->dev, dma_addr, len, DMA_TO_DEVICE);
560 dev_err(nfc->dev, "Error writing page %d\n", page);
599 struct arasan_nfc *nfc = to_anfc(chip->controller);
607 nfc_op->addr2_reg = ADDR2_CS(nfc->native_cs);
680 static int anfc_rw_pio_op(struct arasan_nfc *nfc, struct anfc_op *nfc_op)
690 ret = anfc_wait_for_event(nfc, dir);
692 dev_err(nfc->dev, "PIO %s ready signal not received\n",
699 ioread32_rep(nfc->base + DATA_PORT_REG, &buf[offset],
702 iowrite32_rep(nfc->base + DATA_PORT_REG, &buf[offset],
712 remainder = readl_relaxed(nfc->base + DATA_PORT_REG);
716 writel_relaxed(remainder, nfc->base + DATA_PORT_REG);
720 return anfc_wait_for_event(nfc, XFER_COMPLETE);
727 struct arasan_nfc *nfc = to_anfc(chip->controller);
736 anfc_trigger_op(nfc, &nfc_op);
739 ret = anfc_wait_for_rb(nfc, chip, nfc_op.rdy_timeout_ms);
744 return anfc_rw_pio_op(nfc, &nfc_op);
791 struct arasan_nfc *nfc = to_anfc(chip->controller);
800 anfc_trigger_op(nfc, &nfc_op);
802 ret = anfc_wait_for_event(nfc, XFER_COMPLETE);
807 ret = anfc_wait_for_rb(nfc, chip, nfc_op.rdy_timeout_ms);
815 struct arasan_nfc *nfc = to_anfc(chip->controller);
827 tmp = readl_relaxed(nfc->base + FLASH_STS_REG);
848 struct arasan_nfc *nfc = to_anfc(chip->controller);
856 return anfc_wait_for_rb(nfc, chip, nfc_op.rdy_timeout_ms);
978 struct arasan_nfc *nfc = to_anfc(chip->controller);
979 struct device_node *np = nfc->dev->of_node;
1107 static int anfc_init_hw_ecc_controller(struct arasan_nfc *nfc,
1124 dev_err(nfc->dev, "Unsupported page size %d\n", mtd->writesize);
1146 dev_err(nfc->dev, "Unsupported strength %d\n", ecc->strength);
1160 dev_err(nfc->dev, "Unsupported step size %d\n", ecc->strength);
1176 anand->errloc = devm_kmalloc_array(nfc->dev, ecc->strength,
1181 anand->hw_ecc = devm_kmalloc(nfc->dev, ecc->bytes, GFP_KERNEL);
1199 struct arasan_nfc *nfc = to_anfc(chip->controller);
1246 ret = anfc_init_hw_ecc_controller(nfc, chip);
1249 dev_err(nfc->dev, "Unsupported ECC mode: %d\n",
1272 static int anfc_chip_init(struct arasan_nfc *nfc, struct device_node *np)
1279 anand = devm_kzalloc(nfc->dev, sizeof(*anand), GFP_KERNEL);
1285 if (anand->ncs_idx <= 0 || anand->ncs_idx > nfc->ncs) {
1286 dev_err(nfc->dev, "Invalid reg property\n");
1290 anand->cs_idx = devm_kcalloc(nfc->dev, anand->ncs_idx,
1299 dev_err(nfc->dev, "invalid CS property: %d\n", ret);
1310 dev_err(nfc->dev, "Wrong RB %d\n", rb);
1318 mtd->dev.parent = nfc->dev;
1319 chip->controller = &nfc->controller;
1325 dev_err(nfc->dev, "NAND label property is mandatory\n");
1331 dev_err(nfc->dev, "Scan operation failed\n");
1341 list_add_tail(&anand->node, &nfc->chips);
1346 static void anfc_chips_cleanup(struct arasan_nfc *nfc)
1352 list_for_each_entry_safe(anand, tmp, &nfc->chips, node) {
1361 static int anfc_chips_init(struct arasan_nfc *nfc)
1363 struct device_node *np = nfc->dev->of_node, *nand_np;
1368 dev_err(nfc->dev, "Incorrect number of NAND chips (%d)\n",
1374 ret = anfc_chip_init(nfc, nand_np);
1377 anfc_chips_cleanup(nfc);
1385 static void anfc_reset(struct arasan_nfc *nfc)
1388 writel_relaxed(0, nfc->base + INTR_SIG_EN_REG);
1391 writel_relaxed(EVENT_MASK, nfc->base + INTR_STS_EN_REG);
1393 nfc->cur_cs = -1;
1396 static int anfc_parse_cs(struct arasan_nfc *nfc)
1401 ret = rawnand_dt_parse_gpio_cs(nfc->dev, &nfc->cs_array, &nfc->ncs);
1410 * case, the "not" chosen CS is assigned to nfc->spare_cs and selected
1413 if (nfc->cs_array && nfc->ncs > 2) {
1414 if (!nfc->cs_array[0] && !nfc->cs_array[1]) {
1415 dev_err(nfc->dev,
1420 if (nfc->cs_array[0])
1421 nfc->spare_cs = 0;
1423 nfc->spare_cs = 1;
1426 if (!nfc->cs_array) {
1427 nfc->cs_array = anfc_default_cs_array;
1428 nfc->ncs = ANFC_MAX_CS;
1437 struct arasan_nfc *nfc;
1440 nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), GFP_KERNEL);
1441 if (!nfc)
1444 nfc->dev = &pdev->dev;
1445 nand_controller_init(&nfc->controller);
1446 nfc->controller.ops = &anfc_ops;
1447 INIT_LIST_HEAD(&nfc->chips);
1449 nfc->base = devm_platform_ioremap_resource(pdev, 0);
1450 if (IS_ERR(nfc->base))
1451 return PTR_ERR(nfc->base);
1453 anfc_reset(nfc);
1455 nfc->controller_clk = devm_clk_get_enabled(&pdev->dev, "controller");
1456 if (IS_ERR(nfc->controller_clk))
1457 return PTR_ERR(nfc->controller_clk);
1459 nfc->bus_clk = devm_clk_get_enabled(&pdev->dev, "bus");
1460 if (IS_ERR(nfc->bus_clk))
1461 return PTR_ERR(nfc->bus_clk);
1467 ret = anfc_parse_cs(nfc);
1471 ret = anfc_chips_init(nfc);
1475 platform_set_drvdata(pdev, nfc);
1482 struct arasan_nfc *nfc = platform_get_drvdata(pdev);
1484 anfc_chips_cleanup(nfc);
1492 .compatible = "arasan,nfc-v3p10",