Lines Matching defs:timings
157 * @timings: NV-DDR specific timings to use
178 u32 timings;
344 /* Update the controller timings and the potential ECC configuration */
346 writel_relaxed(anand->timings, nfc->base + TIMING_REG);
999 DIFACE_SDR_MODE(conf->timings.mode);
1000 anand->timings = 0;
1003 DIFACE_DDR_MODE(conf->timings.mode);
1005 if (conf->timings.nvddr.tCCS_min <= 100000)
1007 else if (conf->timings.nvddr.tCCS_min <= 200000)
1009 else if (conf->timings.nvddr.tCCS_min <= 300000)
1015 if (conf->timings.nvddr.tCAD_min < 45000)
1018 switch (conf->timings.mode) {
1038 anand->timings = tccs_min | fast_tcad |
1046 /* ONFI timings are defined in picoseconds */
1048 conf->timings.nvddr.tCK_min);
1058 nand_interface_is_sdr(conf) && conf->timings.mode >= 2)