Lines Matching defs:controller
133 * @read: Data transfer direction from the controller point of view
168 * of the controller structure @gpio_cs array
193 * struct arasan_nfc - Defines the Arasan NAND flash controller driver instance
198 * @controller: Base controller structure
199 * @chips: List of all NAND chips attached to the controller
214 struct nand_controller controller;
231 return container_of(ctrl, struct arasan_nfc, controller);
338 struct arasan_nfc *nfc = to_anfc(chip->controller);
344 /* Update the controller timings and the potential ECC configuration */
371 * When using the embedded hardware ECC engine, the controller is in charge of
377 * 2/ After having read the relevant number of ECC bytes, the controller uses
395 struct arasan_nfc *nfc = to_anfc(chip->controller);
514 struct arasan_nfc *nfc = to_anfc(chip->controller);
599 struct arasan_nfc *nfc = to_anfc(chip->controller);
656 * means the controller might read/write more than
727 struct arasan_nfc *nfc = to_anfc(chip->controller);
764 * and NV-DDR). So, for simplicity, let's program the controller with
791 struct arasan_nfc *nfc = to_anfc(chip->controller);
815 struct arasan_nfc *nfc = to_anfc(chip->controller);
848 struct arasan_nfc *nfc = to_anfc(chip->controller);
910 * The controller abstracts all the NAND operations and do not support
940 * The controller does not allow to proceed with a CMD+DATA_IN cycle
942 * the controller abstract a status read operation with its own status
978 struct arasan_nfc *nfc = to_anfc(chip->controller);
1057 if (of_device_is_compatible(np, "xlnx,zynqmp-nand-controller") &&
1199 struct arasan_nfc *nfc = to_anfc(chip->controller);
1319 chip->controller = &nfc->controller;
1406 * The controller native CS cannot be both disabled at the same time.
1445 nand_controller_init(&nfc->controller);
1446 nfc->controller.ops = &anfc_ops;
1455 nfc->controller_clk = devm_clk_get_enabled(&pdev->dev, "controller");
1489 .compatible = "xlnx,zynqmp-nand-controller",
1500 .name = "arasan-nand-controller",