Lines Matching defs:base
195 * @base: Remapped register area
211 void __iomem *base;
239 ret = readl_relaxed_poll_timeout(nfc->base + INTR_STS_REG, val,
247 writel_relaxed(event, nfc->base + INTR_STS_REG);
260 ret = readl_relaxed_poll_timeout(nfc->base + READY_STS_REG, val,
265 readl_relaxed(nfc->base + READY_STS_REG));
274 writel_relaxed(nfc_op->pkt_reg, nfc->base + PKT_REG);
275 writel_relaxed(nfc_op->addr1_reg, nfc->base + MEM_ADDR1_REG);
276 writel_relaxed(nfc_op->addr2_reg, nfc->base + MEM_ADDR2_REG);
277 writel_relaxed(nfc_op->cmd_reg, nfc->base + CMD_REG);
278 writel_relaxed(nfc_op->prog_reg, nfc->base + PROG_REG);
345 writel_relaxed(anand->data_iface, nfc->base + DATA_INTERFACE_REG);
346 writel_relaxed(anand->timings, nfc->base + TIMING_REG);
429 writel_relaxed(lower_32_bits(dma_addr), nfc->base + DMA_ADDR0_REG);
430 writel_relaxed(upper_32_bits(dma_addr), nfc->base + DMA_ADDR1_REG);
542 writel_relaxed(anand->ecc_conf, nfc->base + ECC_CONF_REG);
545 nfc->base + ECC_SP_REG);
553 writel_relaxed(lower_32_bits(dma_addr), nfc->base + DMA_ADDR0_REG);
554 writel_relaxed(upper_32_bits(dma_addr), nfc->base + DMA_ADDR1_REG);
699 ioread32_rep(nfc->base + DATA_PORT_REG, &buf[offset],
702 iowrite32_rep(nfc->base + DATA_PORT_REG, &buf[offset],
712 remainder = readl_relaxed(nfc->base + DATA_PORT_REG);
716 writel_relaxed(remainder, nfc->base + DATA_PORT_REG);
827 tmp = readl_relaxed(nfc->base + FLASH_STS_REG);
1388 writel_relaxed(0, nfc->base + INTR_SIG_EN_REG);
1391 writel_relaxed(EVENT_MASK, nfc->base + INTR_STS_EN_REG);
1449 nfc->base = devm_platform_ioremap_resource(pdev, 0);
1450 if (IS_ERR(nfc->base))
1451 return PTR_ERR(nfc->base);