Lines Matching refs:mxic
19 #include <linux/mtd/nand-ecc-mxic.h>
174 static void mxic_ecc_disable_engine(struct mxic_ecc_engine *mxic)
178 reg = readl(mxic->regs + DP_CONFIG);
180 writel(reg, mxic->regs + DP_CONFIG);
183 static void mxic_ecc_enable_engine(struct mxic_ecc_engine *mxic)
187 reg = readl(mxic->regs + DP_CONFIG);
189 writel(reg, mxic->regs + DP_CONFIG);
192 static void mxic_ecc_disable_int(struct mxic_ecc_engine *mxic)
194 writel(0, mxic->regs + INTRPT_SIG_EN);
197 static void mxic_ecc_enable_int(struct mxic_ecc_engine *mxic)
199 writel(TRANS_CMPLT, mxic->regs + INTRPT_SIG_EN);
204 struct mxic_ecc_engine *mxic = dev_id;
207 sts = readl(mxic->regs + INTRPT_STS);
212 complete(&mxic->complete);
214 writel(sts, mxic->regs + INTRPT_STS);
221 struct mxic_ecc_engine *mxic = nand_to_mxic(nand);
249 TO_SPARE | TO_MAIN, mxic->regs + INTRPT_STS_EN);
298 writel(ECC_TYP(idx), mxic->regs + DP_CONFIG);
300 spare_reg = readl(mxic->regs + SPARE_SIZE);
326 readl(mxic->regs + DP_VER) >> DP_VER_OFFSET);
327 dev_err(dev, "Chunk size: %d\n", readl(mxic->regs + CHUNK_SIZE));
328 dev_err(dev, "Main size: %d\n", readl(mxic->regs + MAIN_SIZE));
362 struct mxic_ecc_engine *mxic = nand_to_mxic(nand);
373 writel(1, mxic->regs + CHUNK_CNT);
375 mxic->regs + HC_CONFIG);
382 struct mxic_ecc_engine *mxic = nand_to_mxic(nand);
400 writel(ctx->steps, mxic->regs + CHUNK_CNT);
407 mxic->regs + HC_CONFIG);
422 static int mxic_ecc_data_xfer_wait_for_completion(struct mxic_ecc_engine *mxic)
427 if (mxic->irq) {
428 reinit_completion(&mxic->complete);
429 mxic_ecc_enable_int(mxic);
430 ret = wait_for_completion_timeout(&mxic->complete,
433 mxic_ecc_disable_int(mxic);
435 ret = readl_poll_timeout(mxic->regs + INTRPT_STS, val,
437 writel(val, mxic->regs + INTRPT_STS);
441 dev_err(mxic->dev, "Timeout on data xfer completion\n");
448 static int mxic_ecc_process_data(struct mxic_ecc_engine *mxic,
455 mxic_ecc_enable_engine(mxic);
458 writel(SDMA_STRT | dir, mxic->regs + SDMA_CTRL);
461 ret = mxic_ecc_data_xfer_wait_for_completion(mxic);
463 mxic_ecc_disable_engine(mxic);
471 struct mxic_ecc_engine *mxic = pip_ecc_eng_to_mxic(eng);
474 writel(dirmap, mxic->regs + HC_SLV_ADDR);
476 return mxic_ecc_process_data(mxic, direction);
519 static int mxic_ecc_count_biterrs(struct mxic_ecc_engine *mxic,
524 struct device *dev = mxic->dev;
555 struct mxic_ecc_engine *mxic = nand_to_mxic(nand);
576 nents = dma_map_sg(mxic->dev, ctx->sg, 2, DMA_BIDIRECTIONAL);
580 mutex_lock(&mxic->lock);
584 mxic->regs + SDMA_MAIN_ADDR);
586 mxic->regs + SDMA_SPARE_ADDR);
587 ret = mxic_ecc_process_data(mxic, ctx->req->type);
592 mutex_unlock(&mxic->lock);
594 dma_unmap_sg(mxic->dev, ctx->sg, 2, DMA_BIDIRECTIONAL);
615 struct mxic_ecc_engine *mxic = nand_to_mxic(nand);
633 nents = dma_map_sg(mxic->dev, ctx->sg, 2, DMA_BIDIRECTIONAL);
637 mutex_lock(&mxic->lock);
641 mxic->regs + SDMA_MAIN_ADDR);
643 mxic->regs + SDMA_SPARE_ADDR);
644 ret = mxic_ecc_process_data(mxic, ctx->req->type);
649 mutex_unlock(&mxic->lock);
651 dma_unmap_sg(mxic->dev, ctx->sg, 2, DMA_BIDIRECTIONAL);
664 return mxic_ecc_count_biterrs(mxic, nand);
671 struct mxic_ecc_engine *mxic = nand_to_mxic(nand);
688 nents = dma_map_sg(mxic->dev, ctx->sg, 2, DMA_BIDIRECTIONAL);
692 mutex_lock(&mxic->lock);
694 writel(sg_dma_address(&ctx->sg[0]), mxic->regs + SDMA_MAIN_ADDR);
695 writel(sg_dma_address(&ctx->sg[1]), mxic->regs + SDMA_SPARE_ADDR);
703 struct mxic_ecc_engine *mxic = nand_to_mxic(nand);
710 mutex_unlock(&mxic->lock);
712 dma_unmap_sg(mxic->dev, ctx->sg, 2, DMA_BIDIRECTIONAL);
718 ret = mxic_ecc_count_biterrs(mxic, nand);
766 struct mxic_ecc_engine *mxic = pip_ecc_eng_to_mxic(eng);
768 platform_device_put(to_platform_device(mxic->dev));
776 struct mxic_ecc_engine *mxic;
782 mxic = platform_get_drvdata(eng_pdev);
783 if (!mxic) {
788 return &mxic->pipelined_engine;
799 struct mxic_ecc_engine *mxic;
802 mxic = devm_kzalloc(&pdev->dev, sizeof(*mxic), GFP_KERNEL);
803 if (!mxic)
806 mxic->dev = &pdev->dev;
812 mxic->regs = devm_platform_ioremap_resource(pdev, 0);
813 if (IS_ERR(mxic->regs)) {
815 return PTR_ERR(mxic->regs);
818 mxic_ecc_disable_engine(mxic);
819 mxic_ecc_disable_int(mxic);
822 mxic->irq = platform_get_irq_byname_optional(pdev, "ecc-engine");
823 if (mxic->irq > 0) {
824 ret = devm_request_irq(&pdev->dev, mxic->irq, mxic_ecc_isr, 0,
825 "mxic-ecc", mxic);
830 mxic->irq = 0;
833 mutex_init(&mxic->lock);
840 mxic->external_engine.dev = &pdev->dev;
841 mxic->external_engine.integration = NAND_ECC_ENGINE_INTEGRATION_EXTERNAL;
842 mxic->external_engine.ops = &mxic_ecc_engine_external_ops;
844 nand_ecc_register_on_host_hw_engine(&mxic->external_engine);
846 platform_set_drvdata(pdev, mxic);
853 struct mxic_ecc_engine *mxic = platform_get_drvdata(pdev);
855 nand_ecc_unregister_on_host_hw_engine(&mxic->external_engine);
868 .name = "mxic-nand-ecc-engine",