Lines Matching defs:sdmmc_base
186 void __iomem *sdmmc_base;
212 u32 reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);
219 writeb(reg_tmp, priv->sdmmc_base + SDMMC_BUSMODE);
235 tmp_resp = readb(priv->sdmmc_base + SDMMC_RSP);
237 tmp_resp = readb(priv->sdmmc_base + SDMMC_RSP +
249 reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR);
250 writeb(reg_tmp | CTLR_CMD_START, priv->sdmmc_base + SDMMC_CTLR);
262 writeb(command, priv->sdmmc_base + SDMMC_CMD);
263 writel(arg, priv->sdmmc_base + SDMMC_ARG);
264 writeb(rsptype, priv->sdmmc_base + SDMMC_RSPTYPE);
267 reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR);
268 writeb(reg_tmp | CTLR_FIFO_RESET, priv->sdmmc_base + SDMMC_CTLR);
274 writeb(0xFF, priv->sdmmc_base + SDMMC_STS0);
275 writeb(0xFF, priv->sdmmc_base + SDMMC_STS1);
276 writeb(0xFF, priv->sdmmc_base + SDMMC_STS2);
277 writeb(0xFF, priv->sdmmc_base + SDMMC_STS3);
280 reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR);
282 priv->sdmmc_base + SDMMC_CTLR);
289 writel(DMA_ISR_INT_STS, priv->sdmmc_base + SDDMA_ISR);
290 writel(0, priv->sdmmc_base + SDDMA_IER);
340 status = readl(priv->sdmmc_base + SDDMA_CCR) & 0x0F;
380 status0 = readb(priv->sdmmc_base + SDMMC_STS0);
381 status1 = readb(priv->sdmmc_base + SDMMC_STS1);
382 status2 = readb(priv->sdmmc_base + SDMMC_STS2);
385 reg_tmp = readb(priv->sdmmc_base + SDMMC_INTMASK0);
396 writeb(STS0_DEVICE_INS, priv->sdmmc_base + SDMMC_STS0);
454 writeb(status0, priv->sdmmc_base + SDMMC_STS0);
455 writeb(status1, priv->sdmmc_base + SDMMC_STS1);
456 writeb(status2, priv->sdmmc_base + SDMMC_STS2);
469 reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);
470 writeb(reg_tmp | BM_SOFT_RESET, priv->sdmmc_base + SDMMC_BUSMODE);
473 reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR);
474 writeb(reg_tmp | CTLR_FIFO_RESET, priv->sdmmc_base + SDMMC_CTLR);
477 writew(BLKL_INT_ENABLE | BLKL_GPI_CD, priv->sdmmc_base + SDMMC_BLKLEN);
480 writeb(0xFF, priv->sdmmc_base + SDMMC_STS0);
481 writeb(0xFF, priv->sdmmc_base + SDMMC_STS1);
484 writeb(INT0_CD_INT_EN | INT0_DI_INT_EN, priv->sdmmc_base +
487 INT1_CMD_RES_TOUT_INT_EN, priv->sdmmc_base + SDMMC_INTMASK1);
490 writew(8191, priv->sdmmc_base + SDMMC_DMATIMEOUT);
493 reg_tmp = readb(priv->sdmmc_base + SDMMC_STS2);
494 writeb(reg_tmp | STS2_DIS_FORCECLK, priv->sdmmc_base + SDMMC_STS2);
506 writel(DMA_GCR_SOFT_RESET, priv->sdmmc_base + SDDMA_GCR);
507 writel(DMA_GCR_DMA_EN, priv->sdmmc_base + SDDMA_GCR);
508 if ((readl(priv->sdmmc_base + SDDMA_GCR) & DMA_GCR_DMA_EN) != 0)
532 writel(DMA_IER_INT_EN, priv->sdmmc_base + SDDMA_IER);
535 writel(descaddr, priv->sdmmc_base + SDDMA_DESPR);
537 writel(0x00, priv->sdmmc_base + SDDMA_CCR);
540 reg_tmp = readl(priv->sdmmc_base + SDDMA_CCR);
541 writel(reg_tmp & DMA_CCR_IF_TO_PERIPHERAL, priv->sdmmc_base +
544 reg_tmp = readl(priv->sdmmc_base + SDDMA_CCR);
545 writel(reg_tmp | DMA_CCR_PERIPHERAL_TO_IF, priv->sdmmc_base +
554 reg_tmp = readl(priv->sdmmc_base + SDDMA_CCR);
555 writel(reg_tmp | DMA_CCR_RUN, priv->sdmmc_base + SDDMA_CCR);
609 reg_tmp = readw(priv->sdmmc_base + SDMMC_BLKLEN);
611 priv->sdmmc_base + SDMMC_BLKLEN);
614 writew(req->data->blocks, priv->sdmmc_base + SDMMC_BLKCNT);
687 busmode = readb(priv->sdmmc_base + SDMMC_BUSMODE);
688 extctrl = readb(priv->sdmmc_base + SDMMC_EXTCTRL);
705 writeb(busmode, priv->sdmmc_base + SDMMC_BUSMODE);
706 writeb(extctrl, priv->sdmmc_base + SDMMC_EXTCTRL);
713 return !(readb(priv->sdmmc_base + SDMMC_STS0) & STS0_WRITE_PROTECT);
719 u32 cd = (readb(priv->sdmmc_base + SDMMC_STS0) & STS0_CD_GPI) >> 3;
807 priv->sdmmc_base = of_iomap(np, 0);
808 if (!priv->sdmmc_base) {
875 iounmap(priv->sdmmc_base);
892 reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);
893 writel(reg_tmp | BM_SOFT_RESET, priv->sdmmc_base + SDMMC_BUSMODE);
894 reg_tmp = readw(priv->sdmmc_base + SDMMC_BLKLEN);
895 writew(reg_tmp & ~(0xA000), priv->sdmmc_base + SDMMC_BLKLEN);
896 writeb(0xFF, priv->sdmmc_base + SDMMC_STS0);
897 writeb(0xFF, priv->sdmmc_base + SDMMC_STS1);
908 iounmap(priv->sdmmc_base);
929 reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);
930 writeb(reg_tmp | BM_SOFT_RESET, priv->sdmmc_base +
933 reg_tmp = readw(priv->sdmmc_base + SDMMC_BLKLEN);
934 writew(reg_tmp & 0x5FFF, priv->sdmmc_base + SDMMC_BLKLEN);
936 writeb(0xFF, priv->sdmmc_base + SDMMC_STS0);
937 writeb(0xFF, priv->sdmmc_base + SDMMC_STS1);
953 reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);
954 writeb(reg_tmp | BM_SOFT_RESET, priv->sdmmc_base +
957 reg_tmp = readw(priv->sdmmc_base + SDMMC_BLKLEN);
959 priv->sdmmc_base + SDMMC_BLKLEN);
961 reg_tmp = readb(priv->sdmmc_base + SDMMC_INTMASK0);
962 writeb(reg_tmp | INT0_DI_INT_EN, priv->sdmmc_base +