Lines Matching defs:output
235 u32 output;
755 clk_set_phase(host->clk_output, host->cfg->clk_delays[index].output);
1124 [SDXC_CLK_400K] = { .output = 180, .sample = 180 },
1125 [SDXC_CLK_25M] = { .output = 180, .sample = 75 },
1126 [SDXC_CLK_50M] = { .output = 90, .sample = 120 },
1127 [SDXC_CLK_50M_DDR] = { .output = 60, .sample = 120 },
1129 [SDXC_CLK_50M_DDR_8BIT] = { .output = 90, .sample = 180 },
1133 [SDXC_CLK_400K] = { .output = 180, .sample = 180 },
1134 [SDXC_CLK_25M] = { .output = 180, .sample = 75 },
1135 [SDXC_CLK_50M] = { .output = 150, .sample = 120 },
1136 [SDXC_CLK_50M_DDR] = { .output = 54, .sample = 36 },
1137 [SDXC_CLK_50M_DDR_8BIT] = { .output = 72, .sample = 72 },
1253 dev_err(host->dev, "Enable output clk err %d\n", ret);
1330 host->clk_output = devm_clk_get(&pdev->dev, "output");
1332 dev_err(&pdev->dev, "Could not get output clock\n");