Lines Matching defs:ios
723 struct mmc_ios *ios, u32 rate)
741 if (ios->timing != MMC_TIMING_UHS_DDR50 &&
742 ios->timing != MMC_TIMING_MMC_DDR52) {
744 } else if (ios->bus_width == MMC_BUS_WIDTH_8) {
761 struct mmc_ios *ios)
765 u32 rval, clock = ios->clock, div = 1;
775 if (!ios->clock)
787 if (ios->timing == MMC_TIMING_MMC_DDR52 &&
789 ios->bus_width == MMC_BUS_WIDTH_8)) {
843 ret = sunxi_mmc_clk_set_phase(host, ios, rate);
885 static void sunxi_mmc_set_clk(struct sunxi_mmc_host *host, struct mmc_ios *ios)
891 if (ios->timing == MMC_TIMING_UHS_DDR50 ||
892 ios->timing == MMC_TIMING_MMC_DDR52)
898 host->ferror = sunxi_mmc_clk_set_rate(host, ios);
903 struct mmc_ios *ios)
907 switch (ios->power_mode) {
914 ios->vdd);
948 static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
952 sunxi_mmc_card_power(host, ios);
953 sunxi_mmc_set_bus_width(host, ios->bus_width);
954 sunxi_mmc_set_clk(host, ios);
957 static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
963 ret = mmc_regulator_set_vqmmc(mmc, ios);
968 if (mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1516 sunxi_mmc_set_bus_width(host, mmc->ios.bus_width);
1517 sunxi_mmc_set_clk(host, &mmc->ios);