Lines Matching defs:clock
98 /* clock control bits */
254 /* Does DATA0 needs to be masked while the clock is updated */
259 * a mode switch in the clock controller, or the mmc controller
265 /* clock hardware can switch between old and new timing modes */
278 /* clock management */
666 dev_dbg(mmc_dev(host->mmc), "%sabling the clock\n",
750 dev_dbg(mmc_dev(host->mmc), "Invalid clock... returning\n");
765 u32 rval, clock = ios->clock, div = 1;
772 /* Our clock is gated now */
775 if (!ios->clock)
780 * clock to be double the card clock. Under the new timing
781 * mode, all DDR modes require a doubled module clock.
791 clock <<= 1;
803 rate = clk_round_rate(host->clk_mmc, clock);
806 clock, rate);
810 clock, rate);
812 /* setting clock rate */
826 /* update card clock rate to account for internal divider */
842 /* sunxi_mmc_clk_set_phase expects the actual card clock rate */
863 /* And we just enabled our clock back */
1319 dev_err(&pdev->dev, "Could not get ahb clock\n");
1325 dev_err(&pdev->dev, "Could not get mmc clock\n");
1332 dev_err(&pdev->dev, "Could not get output clock\n");
1338 dev_err(&pdev->dev, "Could not get sample clock\n");