Lines Matching refs:timing_cfg0
526 u32 timing_cfg0 = 0;
531 timing_cfg0 = readl(host->base + SPMMC_SD_TIMING_CONFIG0_REG);
533 timing_cfg0);
535 timing_cfg0);
537 timing_cfg0);
539 timing_cfg0);
541 timing_cfg0);
578 timing_cfg0 &= ~SPMMC_SD_READ_CRC_DELAY;
579 timing_cfg0 |= FIELD_PREP(SPMMC_SD_READ_CRC_DELAY,
581 timing_cfg0 &= ~SPMMC_SD_READ_DATA_DELAY;
582 timing_cfg0 |= FIELD_PREP(SPMMC_SD_READ_DATA_DELAY,
584 timing_cfg0 &= ~SPMMC_SD_READ_RESPONSE_DELAY;
585 timing_cfg0 |= FIELD_PREP(SPMMC_SD_READ_RESPONSE_DELAY,
587 timing_cfg0 &= ~SPMMC_SD_WRITE_COMMAND_DELAY;
588 timing_cfg0 |= FIELD_PREP(SPMMC_SD_WRITE_COMMAND_DELAY,
590 timing_cfg0 &= ~SPMMC_SD_WRITE_DATA_DELAY;
591 timing_cfg0 |= FIELD_PREP(SPMMC_SD_WRITE_DATA_DELAY,
593 writel(timing_cfg0, host->base + SPMMC_SD_TIMING_CONFIG0_REG);