Lines Matching defs:sdhci_am654
3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs
170 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
176 regmap_update_bits(sdhci_am654->base, PHY_CTRL5,
179 if (sdhci_am654->flags & FREQSEL_2_BIT) {
197 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);
208 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK,
213 val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT;
217 val |= sdhci_am654->drv_strength << DR_TY_SHIFT;
218 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val);
221 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK,
227 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val,
235 static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654,
239 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK,
241 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK,
243 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0);
246 static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654,
251 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
255 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);
257 sdhci_am654_write_itapdly(sdhci_am654,
258 sdhci_am654->itap_del_sel[timing]);
264 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
270 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
275 if (sdhci_am654->legacy_otapdly)
276 otap_del_sel = sdhci_am654->otap_del_sel[0];
278 otap_del_sel = sdhci_am654->otap_del_sel[timing];
288 if (sdhci_am654->flags & STRBSEL_4_BIT)
293 val |= sdhci_am654->strb_sel << STRBSEL_SHIFT;
296 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
301 sdhci_am654_setup_delay_chain(sdhci_am654, timing);
303 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,
304 sdhci_am654->clkbuf_sel);
311 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
317 if (sdhci_am654->legacy_otapdly)
318 otap_del_sel = sdhci_am654->otap_del_sel[0];
320 otap_del_sel = sdhci_am654->otap_del_sel[timing];
325 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
327 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,
328 sdhci_am654->clkbuf_sel);
379 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
383 if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST) {
424 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
429 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK,
433 sdhci_am654_write_itapdly(sdhci_am654, itap);
452 sdhci_am654_write_itapdly(sdhci_am654, itap);
574 struct sdhci_am654_data *sdhci_am654)
581 &sdhci_am654->otap_del_sel[MMC_TIMING_LEGACY]);
588 &sdhci_am654->otap_del_sel[0]);
596 sdhci_am654->legacy_otapdly = true;
604 &sdhci_am654->otap_del_sel[i]);
620 &sdhci_am654->itap_del_sel[i]);
629 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
637 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0);
639 if (sdhci_am654->flags & DLL_CALIB) {
640 regmap_read(sdhci_am654->base, PHY_STAT1, &val);
643 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
645 ret = regmap_read_poll_timeout(sdhci_am654->base,
655 if (sdhci_am654->flags & IOMUX_PRESENT)
656 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
663 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK,
667 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK,
678 ret = sdhci_am654_get_otap_delay(host, sdhci_am654);
694 struct sdhci_am654_data *sdhci_am654)
700 if (sdhci_am654->flags & DLL_PRESENT) {
702 &sdhci_am654->trm_icp);
713 sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM;
716 sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM;
719 sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM;
722 sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM;
725 sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM;
733 device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel);
735 &sdhci_am654->clkbuf_sel);
738 sdhci_am654->quirks |= SDHCI_AM654_QUIRK_FORCE_CDTEST;
779 struct sdhci_am654_data *sdhci_am654;
795 host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654));
800 sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
801 sdhci_am654->flags = drvdata->flags;
818 sdhci_am654->base = devm_regmap_init_mmio(dev, base,
820 if (IS_ERR(sdhci_am654->base)) {
822 ret = PTR_ERR(sdhci_am654->base);
826 ret = sdhci_am654_get_of_property(pdev, sdhci_am654);
891 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
896 if (sdhci_am654->flags & DLL_CALIB) {
897 regmap_read(sdhci_am654->base, PHY_STAT1, &val);
900 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
902 ret = regmap_read_poll_timeout(sdhci_am654->base,
912 if (sdhci_am654->flags & IOMUX_PRESENT)
913 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
920 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK,
923 regmap_read(sdhci_am654->base, CTL_CFG_3, &val);
926 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK,