Lines Matching defs:clock
209 host->clock = 0;
379 /* force clock reconfiguration */
380 host->clock = 0;
914 if (host->clock && data->timeout_clks) {
918 * data->timeout_clks is in units of clock cycles.
919 * host->clock is in Hz. target_timeout is in us.
923 if (do_div(val, host->clock))
949 freq = mmc->actual_clock ? : host->clock;
1886 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1919 <= clock)
1922 if ((host->max_clk * host->clk_mul / div) <= clock) {
1933 * Divisor can be too small to reach clock
1934 * speed requirement. Then use the base clock.
1942 if (host->max_clk <= clock)
1947 if ((host->max_clk / div) <= clock)
1960 if ((host->max_clk / div) <= clock)
1994 pr_err("%s: Internal clock never stabilised.\n",
2017 pr_err("%s: PLL clock never stabilised.\n",
2032 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
2040 if (clock == 0)
2043 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
2133 * they can apply clock after applying power
2312 * Strength needs updating. Note, clock changes are handled separately.
2351 if (!ios->clock || ios->clock != host->clock) {
2352 turning_on_clk = ios->clock && !host->clock;
2354 host->ops->set_clock(host, ios->clock);
2355 host->clock = ios->clock;
2358 host->clock) {
2361 host->clock / 1000;
2381 * Special case to avoid multiple clock changes during voltage
2415 * Speed Enable to avoid generating clock glitches.
2464 host->ops->set_clock(host, host->clock);
2858 pr_debug("%s: Tuning timeout, falling back to fixed sampling clock\n",
2877 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
3111 host->ops->set_clock(host, host->clock);
3792 host->clock = 0;
3853 /* Force clock and power re-program */
3855 host->clock = 0;
4389 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
4398 * In case of Host Controller v3.00, find out whether clock
4405 * clock mode is not supported, otherwise the actual clock
4423 * Divided Clock Mode minimum clock rate is always less than
4424 * Programmable Clock Mode minimum clock rate.
4441 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",