Lines Matching defs:host
160 void (*set_soc_pad)(struct sdhci_host *host,
203 static int xenon_alloc_emmc_phy(struct sdhci_host *host)
205 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
209 params = devm_kzalloc(mmc_dev(host->mmc), sizeof(*params), GFP_KERNEL);
222 static int xenon_check_stability_internal_clk(struct sdhci_host *host)
228 1100, 20000, false, host, SDHCI_CLOCK_CONTROL);
230 dev_err(mmc_dev(host->mmc), "phy_init: Internal clock never stabilized.\n");
243 static int xenon_emmc_phy_init(struct sdhci_host *host)
247 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
251 int ret = xenon_check_stability_internal_clk(host);
256 reg = sdhci_readl(host, phy_regs->timing_adj);
258 sdhci_writel(host, reg, phy_regs->timing_adj);
276 clock = host->clock;
298 false, host, phy_regs->timing_adj);
300 dev_err(mmc_dev(host->mmc), "eMMC PHY init cannot complete after %d us\n",
309 static void armada_3700_soc_pad_voltage_set(struct sdhci_host *host,
312 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
331 static void xenon_emmc_phy_set_soc_pad(struct sdhci_host *host,
334 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
342 params->pad_ctrl.set_soc_pad(host, signal_voltage);
350 static int xenon_emmc_phy_enable_dll(struct sdhci_host *host)
353 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
358 if (WARN_ON(host->clock <= MMC_HIGH_52_MAX_DTR))
361 reg = sdhci_readl(host, phy_regs->dll_ctrl);
366 reg = sdhci_readl(host, phy_regs->dll_ctrl);
383 sdhci_writel(host, reg, phy_regs->dll_ctrl);
390 if (sdhci_readw(host, XENON_SLOT_EXT_PRESENT_STATE) &
394 dev_err(mmc_dev(host->mmc), "Wait for DLL Lock time-out\n");
406 static int xenon_emmc_phy_config_tuning(struct sdhci_host *host)
408 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
414 if (host->clock <= MMC_HIGH_52_MAX_DTR)
417 ret = xenon_emmc_phy_enable_dll(host);
422 reg = sdhci_readl(host, XENON_SLOT_DLL_CUR_DLY_VAL);
425 dev_warn(mmc_dev(host->mmc),
432 reg = sdhci_readl(host, XENON_SLOT_OP_STATUS_CTRL);
438 sdhci_writel(host, reg, XENON_SLOT_OP_STATUS_CTRL);
443 static void xenon_emmc_phy_disable_strobe(struct sdhci_host *host)
445 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
450 reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL);
452 sdhci_writel(host, reg, XENON_SLOT_EMMC_CTRL);
456 reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL);
458 sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL);
460 reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1);
462 sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1);
467 static void xenon_emmc_phy_strobe_delay_adj(struct sdhci_host *host)
469 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
473 if (WARN_ON(host->timing != MMC_TIMING_MMC_HS400))
476 if (host->clock <= MMC_HIGH_52_MAX_DTR)
479 dev_dbg(mmc_dev(host->mmc), "starts HS400 strobe delay adjustment\n");
481 xenon_emmc_phy_enable_dll(host);
484 reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL);
493 if (host->mmc->ios.enhanced_strobe)
495 sdhci_writel(host, reg, XENON_SLOT_EMMC_CTRL);
499 reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL);
502 sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL);
504 reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1);
507 sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1);
519 static bool xenon_emmc_phy_slow_mode(struct sdhci_host *host,
522 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
529 if (host->clock > MMC_HIGH_52_MAX_DTR)
532 reg = sdhci_readl(host, phy_regs->timing_adj);
566 sdhci_writel(host, reg, phy_regs->timing_adj);
574 static void xenon_emmc_phy_set(struct sdhci_host *host,
578 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
583 dev_dbg(mmc_dev(host->mmc), "eMMC PHY setting starts\n");
586 reg = sdhci_readl(host, phy_regs->pad_ctrl);
591 sdhci_writel(host, reg, phy_regs->pad_ctrl);
595 reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL);
598 sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL);
600 reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1);
603 sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1);
607 xenon_emmc_phy_slow_mode(host, timing);
615 reg = sdhci_readl(host, phy_regs->timing_adj);
620 sdhci_writel(host, reg, phy_regs->timing_adj);
622 if (xenon_emmc_phy_slow_mode(host, timing))
630 reg = sdhci_readl(host, phy_regs->pad_ctrl2);
633 sdhci_writel(host, reg, phy_regs->pad_ctrl2);
639 reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
641 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
643 reg = sdhci_readl(host, phy_regs->func_ctrl);
660 sdhci_writel(host, reg, phy_regs->func_ctrl);
663 reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
665 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
669 sdhci_writel(host, phy_regs->logic_timing_val,
672 xenon_emmc_phy_disable_strobe(host);
675 xenon_emmc_phy_init(host);
677 dev_dbg(mmc_dev(host->mmc), "eMMC PHY setting completes\n");
680 static int get_dt_pad_ctrl_data(struct sdhci_host *host,
684 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
696 dev_err(mmc_dev(host->mmc), "Unable to find SoC PAD ctrl register address for %pOFn\n",
701 params->pad_ctrl.reg = devm_ioremap_resource(mmc_dev(host->mmc),
708 dev_err(mmc_dev(host->mmc), "Unable to determine SoC PHY PAD ctrl type\n");
716 dev_err(mmc_dev(host->mmc), "Unsupported SoC PHY PAD ctrl type %s\n",
724 static int xenon_emmc_phy_parse_params(struct sdhci_host *host,
753 return get_dt_pad_ctrl_data(host, dev->of_node, params);
758 void xenon_soc_pad_ctrl(struct sdhci_host *host,
761 xenon_emmc_phy_set_soc_pad(host, signal_voltage);
769 static int xenon_hs_delay_adj(struct sdhci_host *host)
773 if (WARN_ON(host->clock <= XENON_DEFAULT_SDCLK_FREQ))
776 switch (host->timing) {
778 xenon_emmc_phy_strobe_delay_adj(host);
782 return xenon_emmc_phy_config_tuning(host);
788 * It is hard to implement such a scan in host driver
789 * since initiating commands by host driver is not safe.
796 dev_warn_once(mmc_dev(host->mmc), "Timing issue might occur in DDR mode\n");
810 int xenon_phy_adj(struct sdhci_host *host, struct mmc_ios *ios)
812 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
816 if (!host->clock) {
826 if ((host->clock == priv->clock) &&
831 xenon_emmc_phy_set(host, ios->timing);
837 priv->clock = host->clock;
843 if (host->clock > XENON_DEFAULT_SDCLK_FREQ)
844 ret = xenon_hs_delay_adj(host);
848 static int xenon_add_phy(struct device *dev, struct sdhci_host *host,
851 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
857 dev_err(mmc_dev(host->mmc),
863 ret = xenon_alloc_emmc_phy(host);
867 return xenon_emmc_phy_parse_params(host, dev, priv->phy_params);
870 int xenon_phy_parse_params(struct device *dev, struct sdhci_host *host)
875 return xenon_add_phy(dev, host, phy_type);
877 return xenon_add_phy(dev, host, "emmc 5.1 phy");