Lines Matching defs:clock
122 * NVQUIRK_HAS_TMCLK is for SoC's having separate timeout clock for Tegra
748 static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
756 if (!clock)
757 return sdhci_set_clock(host, clock);
761 * divider to be configured to divided the host clock by two. The SDHCI
762 * clock divider is calculated as part of sdhci_set_clock() by
764 * the requested clock rate.
766 * By setting the host->max_clk to clock * 2 the divider calculation
768 * regardless of clock rate rounding, which may happen if the value
771 host_clk = tegra_host->ddr_signaling ? clock * 2 : clock;
784 sdhci_set_clock(host, clock);
807 * interface clock to MMC_HS200_MAX_DTR (200 MHz) so that host
808 * controller CAR clock and the interface clock are rate matched.
1724 * Tegra210 has a separate SDMMC_LEGACY_TM clock used for host
1725 * timeout clock and SW can choose TMCLK or SDCLK for hardware
1763 "failed to get clock\n");