Lines Matching refs:scratch_32
169 u32 scratch_32;
172 O2_SD_PLL_SETTING, &scratch_32);
174 scratch_32 &= 0x0000FFFF;
175 scratch_32 |= value;
178 O2_SD_PLL_SETTING, scratch_32);
248 u32 scratch_32 = 0;
263 scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
264 scratch_32 |= O2_PLL_SOFT_RESET;
265 sdhci_writel(host, scratch_32, O2_PLL_DLL_WDT_CONTROL1);
269 &scratch_32);
271 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
272 pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG4, scratch_32);
434 u32 scratch_32;
438 O2_SD_FUNC_REG0, &scratch_32);
442 scratch_32 &= ~O2_SD_FREG0_LEDOFF;
444 O2_SD_FUNC_REG0, scratch_32);
447 O2_SD_TEST_REG, &scratch_32);
451 scratch_32 |= O2_SD_LED_ENABLE;
453 O2_SD_TEST_REG, scratch_32);
458 u32 scratch_32;
461 ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32);
464 scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14));
465 pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32);
468 ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32);
471 scratch_32 &= ~((1 << 19) | (1 << 11));
472 scratch_32 |= (1 << 10);
473 pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32);
476 ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32);
479 scratch_32 |= (1 << 4);
480 pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32);
486 ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32);
489 scratch_32 &= ~(3 << 12);
490 pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32);
493 ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32);
496 scratch_32 &= ~(0x01FE);
497 scratch_32 |= 0x00CC;
498 pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32);
501 O2_SD_TUNING_CTRL, &scratch_32);
504 scratch_32 &= ~(0x000000FF);
505 scratch_32 |= 0x00000066;
506 pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32);
510 O2_SD_UHS2_L1_CTRL, &scratch_32);
513 scratch_32 &= ~(0x000000FC);
514 scratch_32 |= 0x00000084;
515 pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32);
518 ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32);
521 scratch_32 &= ~((1 << 21) | (1 << 30));
523 pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32);
526 ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32);
529 scratch_32 &= ~(0xf0000000);
530 scratch_32 |= 0x30000000;
531 pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32);
534 O2_SD_MISC_CTRL4, &scratch_32);
537 scratch_32 &= ~(0x000f0000);
538 scratch_32 |= 0x00080000;
539 pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32);
582 u32 scratch_32;
611 pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32);
613 if ((scratch_32 & 0xFFFF0000) != dmdn_208m)
616 pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32);
618 if ((scratch_32 & 0xFFFF0000) != dmdn_200m)
622 pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &scratch_32);
623 scratch_32 &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK);
624 pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, scratch_32);
700 u32 scratch_32 = 0;
712 pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &scratch_32);
713 scratch_32 &= ~(O2_SD_SEL_DLL);
714 pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, scratch_32);
815 u32 scratch_32;
887 &scratch_32);
890 scratch_32 = ((scratch_32 & 0xFF000000) >> 24);
893 if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) {
894 scratch_32 = 0x25100000;
896 o2_pci_set_baseclk(chip, scratch_32);
899 &scratch_32);
904 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
907 scratch_32);
922 O2_SD_CLK_SETTING, &scratch_32);
926 scratch_32 &= ~(0xFF00);
927 scratch_32 |= 0x07E0C800;
929 O2_SD_CLK_SETTING, scratch_32);
932 O2_SD_CLKREQ, &scratch_32);
935 scratch_32 |= 0x3;
936 pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32);
939 O2_SD_PLL_SETTING, &scratch_32);
943 scratch_32 &= ~(0x1F3F070E);
944 scratch_32 |= 0x18270106;
946 O2_SD_PLL_SETTING, scratch_32);
950 O2_SD_CAP_REG2, &scratch_32);
953 scratch_32 &= ~(0xE0);
955 O2_SD_CAP_REG2, scratch_32);
980 O2_SD_PLL_SETTING, &scratch_32);
984 if ((scratch_32 & 0xff000000) == 0x01000000) {
985 scratch_32 &= 0x0000FFFF;
986 scratch_32 |= 0x1F340000;
989 O2_SD_PLL_SETTING, scratch_32);
991 scratch_32 &= 0x0000FFFF;
992 scratch_32 |= 0x25100000;
995 O2_SD_PLL_SETTING, scratch_32);
999 &scratch_32);
1002 scratch_32 |= (1 << 22);
1004 O2_SD_FUNC_REG4, scratch_32);
1011 pci_read_config_dword(chip->pdev, O2_SD_MISC_CTRL2, &scratch_32);
1012 scratch_32 &= 0xFFE7FFFF;
1013 scratch_32 |= 0x00180000;
1014 pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL2, scratch_32);
1052 pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &scratch_32);
1053 scratch_32 &= 0xFF0FFF00;
1054 scratch_32 |= 0x00B0003B;
1055 pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, scratch_32);