Lines Matching defs:host
11 #include <linux/mmc/host.h>
84 static void sdhci_o2_wait_card_detect_stable(struct sdhci_host *host)
94 scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE);
101 mmc_hostname(host->mmc));
102 sdhci_dumpregs(host);
109 static void sdhci_o2_enable_internal_clock(struct sdhci_host *host)
116 scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
118 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
121 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
125 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
132 scratch = sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1);
137 mmc_hostname(host->mmc));
138 sdhci_dumpregs(host);
146 sdhci_o2_wait_card_detect_stable(host);
150 scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
152 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
157 struct sdhci_host *host = mmc_priv(mmc);
159 if (!(sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1) & O2_PLL_LOCK_STATUS))
160 sdhci_o2_enable_internal_clock(host);
162 sdhci_o2_wait_card_detect_stable(host);
164 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
181 static u32 sdhci_o2_pll_dll_wdt_control(struct sdhci_host *host)
183 return sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
192 static int sdhci_o2_wait_dll_detect_lock(struct sdhci_host *host)
196 return readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host,
200 static void sdhci_o2_set_tuning_mode(struct sdhci_host *host)
205 reg = sdhci_readw(host, O2_SD_VENDOR_SETTING);
207 sdhci_writew(host, reg, O2_SD_VENDOR_SETTING);
210 static void __sdhci_o2_execute_tuning(struct sdhci_host *host, u32 opcode)
214 sdhci_send_tuning(host, opcode);
217 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
221 host->tuning_done = true;
225 mmc_hostname(host->mmc));
233 mmc_hostname(host->mmc));
234 sdhci_reset_tuning(host);
244 static int sdhci_o2_dll_recovery(struct sdhci_host *host)
249 struct sdhci_pci_slot *slot = sdhci_priv(host);
260 sdhci_writeb(host, 0, SDHCI_CLOCK_CONTROL);
263 scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
265 sdhci_writel(host, scratch_32, O2_PLL_DLL_WDT_CONTROL1);
277 sdhci_writeb(host, scratch_8, SDHCI_CLOCK_CONTROL);
279 if (sdhci_o2_get_cd(host->mmc)) {
285 if (sdhci_o2_wait_dll_detect_lock(host)) {
287 sdhci_writeb(host, scratch_8,
292 mmc_hostname(host->mmc),
297 mmc_hostname(host->mmc));
305 mmc_hostname(host->mmc));
316 struct sdhci_host *host = mmc_priv(mmc);
317 struct sdhci_pci_slot *slot = sdhci_priv(host);
329 if ((host->timing != MMC_TIMING_MMC_HS200) &&
330 (host->timing != MMC_TIMING_UHS_SDR104) &&
331 (host->timing != MMC_TIMING_UHS_SDR50))
338 scratch = sdhci_readw(host, O2_SD_MISC_CTRL);
340 sdhci_writew(host, scratch, O2_SD_MISC_CTRL);
350 reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
352 sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL);
354 if (host->timing == MMC_TIMING_MMC_HS200 ||
355 host->timing == MMC_TIMING_UHS_SDR104) {
374 reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
376 sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL);
383 if (readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host,
386 mmc_hostname(host->mmc));
391 if (!sdhci_o2_wait_dll_detect_lock(host))
392 if (!sdhci_o2_dll_recovery(host)) {
394 mmc_hostname(host->mmc));
398 * o2 sdhci host didn't support 8bit emmc tuning
403 sdhci_set_bus_width(host, MMC_BUS_WIDTH_4);
406 sdhci_o2_set_tuning_mode(host);
408 sdhci_start_tuning(host);
410 __sdhci_o2_execute_tuning(host, opcode);
412 sdhci_end_tuning(host);
416 sdhci_set_bus_width(host, current_bus_width);
420 scratch = sdhci_readw(host, O2_SD_MISC_CTRL);
422 sdhci_writew(host, scratch, O2_SD_MISC_CTRL);
424 sdhci_reset(host, SDHCI_RESET_CMD);
425 sdhci_reset(host, SDHCI_RESET_DATA);
427 host->flags &= ~SDHCI_HS400_TUNING;
436 /* Set led of SD host function enable */
492 /* Set Max power supply capability of SD host */
543 struct sdhci_host *host)
550 mmc_hostname(host->mmc));
558 mmc_hostname(host->mmc), ret);
562 host->irq = pci_irq_vector(chip->pdev, 0);
565 static void sdhci_o2_enable_clk(struct sdhci_host *host, u16 clk)
569 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
571 sdhci_o2_enable_internal_clock(host);
572 if (sdhci_o2_get_cd(host->mmc)) {
574 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
578 static void sdhci_pci_o2_set_clock(struct sdhci_host *host, unsigned int clock)
584 struct sdhci_pci_slot *slot = sdhci_priv(host);
587 host->mmc->actual_clock = 0;
589 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
610 if ((host->timing == MMC_TIMING_UHS_SDR104) && (clock == 200000000)) {
631 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
632 sdhci_o2_enable_clk(host, clk);
637 struct sdhci_host *host = mmc_priv(mmc);
638 struct sdhci_pci_slot *slot = sdhci_priv(host);
645 sdhci_writeb(host, 0, SDHCI_CLOCK_CONTROL);
648 scratch8 = sdhci_readb(host, SDHCI_POWER_CONTROL);
650 if (host->mmc->ios.timing == MMC_TIMING_SD_EXP_1_2V &&
651 host->mmc->caps2 & MMC_CAP2_SD_EXP_1_2V) {
657 sdhci_writeb(host, scratch8, SDHCI_POWER_CONTROL);
666 1, 30000, false, host, O2_SD_EXP_INT_REG);
670 scratch16 = sdhci_readw(host, O2_SD_PCIE_SWITCH);
672 sdhci_writew(host, scratch16, O2_SD_PCIE_SWITCH);
675 scratch8 = sdhci_readb(host, SDHCI_POWER_CONTROL);
677 sdhci_writeb(host, scratch8, SDHCI_POWER_CONTROL);
684 host->mmc->ios.timing = MMC_TIMING_LEGACY;
686 mmc_hostname(host->mmc));
696 static void sdhci_pci_o2_set_power(struct sdhci_host *host, unsigned char mode, unsigned short vdd)
699 struct sdhci_pci_slot *slot = sdhci_priv(host);
722 sdhci_set_power(host, mode, vdd);
728 struct sdhci_host *host;
734 host = slot->host;
737 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
744 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
746 host->quirks2 |= SDHCI_QUIRK2_BROKEN_DDR50;
748 sdhci_pci_o2_enable_msi(chip, host);
750 host->mmc_host_ops.execute_tuning = sdhci_o2_execute_tuning;
757 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING);
759 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
768 mmc_hostname(host->mmc));
769 host->flags &= ~SDHCI_SIGNALING_330;
770 host->flags |= SDHCI_SIGNALING_180;
771 host->mmc->caps2 |= MMC_CAP2_NO_SD;
772 host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
777 slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd;
781 slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd;
782 host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
783 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
789 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2);
791 sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2);
797 host->mmc->caps2 |= MMC_CAP2_NO_SDIO | MMC_CAP2_SD_EXP | MMC_CAP2_SD_EXP_1_2V;
798 host->mmc->caps |= MMC_CAP_HW_RESET;
799 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
800 slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd;
801 host->mmc_host_ops.init_sd_express = sdhci_pci_o2_init_sd_express;
1047 /* Set host drive strength*/