Lines Matching refs:pdev
549 struct pci_dev *pdev;
552 pdev = slot->chip->pdev;
564 pci_read_config_dword(pdev, PCI_GLI_9750_PM_CTRL, &value);
566 pci_write_config_dword(pdev, PCI_GLI_9750_PM_CTRL, value);
568 pci_write_config_dword(pdev, PCI_GLI_9750_PM_CTRL, value);
571 pci_read_config_dword(pdev, PCI_GLI_9750_CORRERR_MASK, &value);
573 pci_write_config_dword(pdev, PCI_GLI_9750_CORRERR_MASK, value);
582 ret = pci_alloc_irq_vectors(slot->chip->pdev, 1, 1,
590 slot->host->irq = pci_irq_vector(slot->chip->pdev, 0);
593 static inline void gl9755_wt_on(struct pci_dev *pdev)
598 pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value);
607 pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value);
610 static inline void gl9755_wt_off(struct pci_dev *pdev)
615 pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value);
624 pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value);
627 static void gl9755_disable_ssc_pll(struct pci_dev *pdev)
631 gl9755_wt_on(pdev);
632 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
634 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
635 gl9755_wt_off(pdev);
638 static void gl9755_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv)
642 gl9755_wt_on(pdev);
643 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
650 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
651 gl9755_wt_off(pdev);
657 static bool gl9755_ssc_enable(struct pci_dev *pdev)
662 gl9755_wt_on(pdev);
663 pci_read_config_dword(pdev, PCI_GLI_9755_MISC, &misc);
665 gl9755_wt_off(pdev);
670 static void gl9755_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm)
675 gl9755_wt_on(pdev);
676 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
677 pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc);
684 pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc);
685 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
686 gl9755_wt_off(pdev);
689 static void gl9755_set_ssc_pll_205mhz(struct pci_dev *pdev)
691 bool enable = gl9755_ssc_enable(pdev);
694 gl9755_set_ssc(pdev, enable, 0xF, 0x5A1D);
695 gl9755_set_pll(pdev, 0x1, 0x246, 0x0);
698 static void gl9755_set_ssc_pll_100mhz(struct pci_dev *pdev)
700 bool enable = gl9755_ssc_enable(pdev);
703 gl9755_set_ssc(pdev, enable, 0xE, 0x51EC);
704 gl9755_set_pll(pdev, 0x1, 0x244, 0x1);
707 static void gl9755_set_ssc_pll_50mhz(struct pci_dev *pdev)
709 bool enable = gl9755_ssc_enable(pdev);
712 gl9755_set_ssc(pdev, enable, 0xE, 0x51EC);
713 gl9755_set_pll(pdev, 0x1, 0x244, 0x3);
720 struct pci_dev *pdev;
723 pdev = slot->chip->pdev;
726 gl9755_disable_ssc_pll(pdev);
735 gl9755_set_ssc_pll_205mhz(pdev);
737 gl9755_set_ssc_pll_100mhz(pdev);
739 gl9755_set_ssc_pll_50mhz(pdev);
747 struct pci_dev *pdev = slot->chip->pdev;
750 gl9755_wt_on(pdev);
752 pci_read_config_dword(pdev, PCI_GLI_9755_PECONF, &value);
757 if (of_property_read_bool(pdev->dev.of_node, "cd-inverted"))
759 if (of_property_read_bool(pdev->dev.of_node, "wp-inverted"))
763 pci_write_config_dword(pdev, PCI_GLI_9755_PECONF, value);
766 pci_read_config_dword(pdev, PCI_GLI_9755_SerDes, &value);
768 pci_write_config_dword(pdev, PCI_GLI_9755_SerDes, value);
770 pci_read_config_dword(pdev, PCI_GLI_9755_CFG2, &value);
775 pci_write_config_dword(pdev, PCI_GLI_9755_CFG2, value);
778 pci_read_config_dword(pdev, PCI_GLI_9755_PM_CTRL, &value);
780 pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value);
782 pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value);
785 pci_read_config_dword(pdev, PCI_GLI_9755_CORRERR_MASK, &value);
787 pci_write_config_dword(pdev, PCI_GLI_9755_CORRERR_MASK, value);
789 gl9755_wt_off(pdev);
792 static inline void gl9767_vhs_read(struct pci_dev *pdev)
797 pci_read_config_dword(pdev, PCIE_GLI_9767_VHS, &vhs_value);
806 pci_write_config_dword(pdev, PCIE_GLI_9767_VHS, vhs_value);
809 static inline void gl9767_vhs_write(struct pci_dev *pdev)
814 pci_read_config_dword(pdev, PCIE_GLI_9767_VHS, &vhs_value);
823 pci_write_config_dword(pdev, PCIE_GLI_9767_VHS, vhs_value);
826 static bool gl9767_ssc_enable(struct pci_dev *pdev)
831 gl9767_vhs_write(pdev);
833 pci_read_config_dword(pdev, PCIE_GLI_9767_COM_MAILBOX, &value);
836 gl9767_vhs_read(pdev);
841 static void gl9767_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm)
846 gl9767_vhs_write(pdev);
848 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll);
849 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, &ssc);
856 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, ssc);
857 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll);
859 gl9767_vhs_read(pdev);
862 static void gl9767_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv)
866 gl9767_vhs_write(pdev);
868 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll);
875 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll);
877 gl9767_vhs_read(pdev);
883 static void gl9767_set_ssc_pll_205mhz(struct pci_dev *pdev)
885 bool enable = gl9767_ssc_enable(pdev);
888 gl9767_set_ssc(pdev, enable, 0x1F, 0xF5C3);
889 gl9767_set_pll(pdev, 0x1, 0x246, 0x0);
892 static void gl9767_disable_ssc_pll(struct pci_dev *pdev)
896 gl9767_vhs_write(pdev);
898 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll);
900 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll);
902 gl9767_vhs_read(pdev);
909 struct pci_dev *pdev;
913 pdev = slot->chip->pdev;
916 gl9767_vhs_write(pdev);
918 pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value);
920 pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value);
922 gl9767_disable_ssc_pll(pdev);
931 gl9767_set_ssc_pll_205mhz(pdev);
936 pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value);
938 pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value);
940 gl9767_vhs_read(pdev);
954 struct pci_dev *pdev = slot->chip->pdev;
957 gl9767_vhs_write(pdev);
959 pci_read_config_dword(pdev, PCIE_GLI_9767_PWR_MACRO_CTL, &value);
969 pci_write_config_dword(pdev, PCIE_GLI_9767_PWR_MACRO_CTL, value);
971 pci_read_config_dword(pdev, PCIE_GLI_9767_SCR, &value);
981 pci_write_config_dword(pdev, PCIE_GLI_9767_SCR, value);
983 gl9767_vhs_read(pdev);
996 struct pci_dev *pdev;
1000 pdev = slot->chip->pdev;
1007 gl9767_vhs_write(pdev);
1009 pci_read_config_dword(pdev, PCIE_GLI_9767_COMBO_MUX_CTL, &value);
1011 pci_write_config_dword(pdev, PCIE_GLI_9767_COMBO_MUX_CTL, value);
1013 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, &value);
1017 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, value);
1019 pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, &value);
1021 pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, value);
1023 pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2, &value);
1025 pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2, value);
1027 pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2, &value);
1029 pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2, value);
1031 pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value);
1033 pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value);
1043 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, &value);
1045 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, value);
1049 pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, &value);
1051 pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2,
1057 pci_read_config_dword(pdev, PCIE_GLI_9767_SDHC_CAP, &value);
1059 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, &value);
1061 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, value);
1074 gl9767_vhs_read(pdev);
1195 struct pci_dev *pdev = slot->chip->pdev;
1198 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
1201 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
1203 pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG, &value);
1210 pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG, value);
1212 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
1215 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
1295 struct device *dev = &slot->chip->pdev->dev;
1338 struct pci_dev *pdev = slot->chip->pdev;
1341 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
1344 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
1346 pci_read_config_dword(pdev, PCIE_GLI_9763E_SCR, &value);
1348 pci_write_config_dword(pdev, PCIE_GLI_9763E_SCR, value);
1350 pci_read_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, &value);
1352 pci_write_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, value);
1354 pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value);
1358 pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value);
1360 pci_read_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, &value);
1363 pci_write_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, value);
1365 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
1368 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
1426 pci_free_irq_vectors(slot->chip->pdev);
1487 struct pci_dev *pdev = slot->chip->pdev;
1500 pci_read_config_dword(pdev, PCIE_GLI_9763E_MB, &value);