Lines Matching defs:host
93 static int arasan_phy_addr_poll(struct sdhci_host *host, u32 offset, u32 mask)
101 val = sdhci_readw(host, PHY_ADDR_REG);
109 static int arasan_phy_write(struct sdhci_host *host, u8 data, u8 offset)
111 sdhci_writew(host, data, PHY_DAT_REG);
112 sdhci_writew(host, (PHY_WRITE | offset), PHY_ADDR_REG);
113 return arasan_phy_addr_poll(host, PHY_ADDR_REG, PHY_BUSY);
116 static int arasan_phy_read(struct sdhci_host *host, u8 offset, u8 *data)
120 sdhci_writew(host, 0, PHY_DAT_REG);
121 sdhci_writew(host, offset, PHY_ADDR_REG);
122 ret = arasan_phy_addr_poll(host, PHY_ADDR_REG, PHY_BUSY);
125 *data = sdhci_readw(host, PHY_DAT_REG) & DATA_MASK;
129 static int arasan_phy_sts_poll(struct sdhci_host *host, u32 offset, u32 mask)
138 ret = arasan_phy_read(host, offset, &val);
149 static int arasan_phy_init(struct sdhci_host *host)
155 if (arasan_phy_read(host, IPAD_CTRL1, &val) ||
156 arasan_phy_write(host, val | RETB_ENBL | PDB_ENBL, IPAD_CTRL1) ||
157 arasan_phy_read(host, IPAD_CTRL2, &val) ||
158 arasan_phy_write(host, val | RTRIM_EN, IPAD_CTRL2))
160 ret = arasan_phy_sts_poll(host, IPAD_STS, CALDONE_MASK);
165 if (arasan_phy_read(host, IOREN_CTRL1, &val) ||
166 arasan_phy_write(host, val | REN_CMND | REN_STRB, IOREN_CTRL1) ||
167 arasan_phy_read(host, IOPU_CTRL1, &val) ||
168 arasan_phy_write(host, val | PU_CMD, IOPU_CTRL1) ||
169 arasan_phy_read(host, CMD_CTRL, &val) ||
170 arasan_phy_write(host, val | PDB_CMND, CMD_CTRL) ||
171 arasan_phy_read(host, IOREN_CTRL2, &val) ||
172 arasan_phy_write(host, val | REN_DATA, IOREN_CTRL2) ||
173 arasan_phy_read(host, IOPU_CTRL2, &val) ||
174 arasan_phy_write(host, val | PU_DAT, IOPU_CTRL2) ||
175 arasan_phy_read(host, DATA_CTRL, &val) ||
176 arasan_phy_write(host, val | PDB_DATA, DATA_CTRL) ||
177 arasan_phy_read(host, STRB_CTRL, &val) ||
178 arasan_phy_write(host, val | PDB_STRB, STRB_CTRL) ||
179 arasan_phy_read(host, CLK_CTRL, &val) ||
180 arasan_phy_write(host, val | PDB_CLOCK, CLK_CTRL) ||
181 arasan_phy_read(host, CLKBUF_SEL, &val) ||
182 arasan_phy_write(host, val | MAX_CLK_BUF, CLKBUF_SEL) ||
183 arasan_phy_write(host, LEGACY_MODE, MODE_CTRL))
189 static int arasan_phy_set(struct sdhci_host *host, u8 mode, u8 otap,
196 ret = arasan_phy_write(host, 0x0, MODE_CTRL);
198 ret = arasan_phy_write(host, mode, MODE_CTRL);
202 ret = arasan_phy_read(host, IPAD_CTRL1, &val);
205 ret = arasan_phy_write(host, IOPAD(val, drv_type), IPAD_CTRL1);
210 ret = arasan_phy_write(host, 0x0, OTAP_DELAY);
213 ret = arasan_phy_write(host, 0x0, ITAP_DELAY);
215 ret = arasan_phy_write(host, OTAPDLY(otap), OTAP_DELAY);
219 ret = arasan_phy_write(host, ITAPDLY(itap), ITAP_DELAY);
221 ret = arasan_phy_write(host, 0x0, ITAP_DELAY);
226 ret = arasan_phy_write(host, trim, DLL_TRIM);
230 ret = arasan_phy_write(host, 0, DLL_STATUS);
234 ret = arasan_phy_write(host, FREQSEL(clk), DLL_STATUS);
237 ret = arasan_phy_sts_poll(host, DLL_STATUS, DLL_RDY_MASK);
244 static int arasan_select_phy_clock(struct sdhci_host *host)
246 struct sdhci_pci_slot *slot = sdhci_priv(host);
250 if (arasan_host->chg_clk == host->mmc->ios.clock)
253 arasan_host->chg_clk = host->mmc->ios.clock;
254 if (host->mmc->ios.clock == 200000000)
256 else if (host->mmc->ios.clock == 100000000)
258 else if (host->mmc->ios.clock == 50000000)
263 if (host->mmc_host_ops.hs400_enhanced_strobe) {
264 arasan_phy_set(host, ENHSTRB_MODE, 1, 0x0, 0x0,
267 switch (host->mmc->ios.timing) {
269 arasan_phy_set(host, LEGACY_MODE, 0x0, 0x0, 0x0,
274 arasan_phy_set(host, HISPD_MODE, 0x3, 0x0, 0x2,
279 arasan_phy_set(host, HS200_MODE, 0x2,
280 host->mmc->ios.drv_type, 0x0,
285 arasan_phy_set(host, DDR50_MODE, 0x1, 0x0,
289 arasan_phy_set(host, HS400_MODE, 0x1,
290 host->mmc->ios.drv_type, 0xa,
304 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | MMC_CAP_8_BIT_DATA;
305 err = arasan_phy_init(slot->host);
311 static void arasan_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
313 sdhci_set_clock(host, clock);
316 arasan_select_phy_clock(host);