Lines Matching refs:state
618 dev_err(dev, "failed to select pinctrl state\n");
1103 dev_err(dev, "no pinctrl state for %s mode", mode);
1119 struct pinctrl_state *state;
1138 state = pinctrl_lookup_state(omap_host->pinctrl, "default");
1139 if (IS_ERR(state)) {
1140 dev_err(dev, "no pinctrl state for default mode\n");
1141 return PTR_ERR(state);
1143 pinctrl_state[MMC_TIMING_LEGACY] = state;
1145 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr104", caps,
1147 if (!IS_ERR(state))
1148 pinctrl_state[MMC_TIMING_UHS_SDR104] = state;
1150 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr50", caps,
1152 if (!IS_ERR(state))
1153 pinctrl_state[MMC_TIMING_UHS_DDR50] = state;
1155 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr50", caps,
1157 if (!IS_ERR(state))
1158 pinctrl_state[MMC_TIMING_UHS_SDR50] = state;
1160 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr25", caps,
1162 if (!IS_ERR(state))
1163 pinctrl_state[MMC_TIMING_UHS_SDR25] = state;
1165 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr12", caps,
1167 if (!IS_ERR(state))
1168 pinctrl_state[MMC_TIMING_UHS_SDR12] = state;
1170 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_1_8v", caps,
1172 if (!IS_ERR(state)) {
1173 pinctrl_state[MMC_TIMING_MMC_DDR52] = state;
1175 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_3_3v",
1178 if (!IS_ERR(state))
1179 pinctrl_state[MMC_TIMING_MMC_DDR52] = state;
1182 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps,
1184 if (!IS_ERR(state))
1185 pinctrl_state[MMC_TIMING_SD_HS] = state;
1187 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps,
1189 if (!IS_ERR(state))
1190 pinctrl_state[MMC_TIMING_MMC_HS] = state;
1192 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs200_1_8v", caps2,
1194 if (!IS_ERR(state))
1195 pinctrl_state[MMC_TIMING_MMC_HS200] = state;