Lines Matching refs:value
75 static void sparx5_set_cacheable(struct sdhci_host *host, u32 value)
80 pr_debug("%s: Set Cacheable = 0x%x\n", mmc_hostname(host->mmc), value);
84 CPU_REGS_PROC_CTRL, ACP_CACHE_MASK, value);
87 static void sparx5_set_delay(struct sdhci_host *host, u8 value)
92 pr_debug("%s: Set DLY_CC = %u\n", mmc_hostname(host->mmc), value);
98 (value << MSHC_DLY_CC_SHIFT));
104 u8 value;
106 value = sdhci_readb(host, MSHC2_EMMC_CTRL);
107 if (!(value & MSHC2_EMMC_CTRL_IS_EMMC)) {
108 value |= MSHC2_EMMC_CTRL_IS_EMMC;
110 mmc_hostname(host->mmc), value);
111 sdhci_writeb(host, value, MSHC2_EMMC_CTRL);
118 u8 value;
121 value = sdhci_readb(host, MSHC2_EMMC_CTRL) &
123 sdhci_writeb(host, value, MSHC2_EMMC_CTRL);
126 sdhci_writeb(host, value | MSHC2_EMMC_CTRL_EMMC_RST_N,
166 u32 value;
194 if (!of_property_read_u32(np, "microchip,clock-delay", &value) &&
195 (value > 0 && value <= MSHC_DLY_CC_MAX))
196 sdhci_sparx5->delay_clock = value;