Lines Matching refs:value
101 * esdhc_readl_fixup - Fixup the value read from incompatible eSDHC register
106 * @value: 32bit eSDHC register value on spec_reg address
113 * Return a fixed up register value
116 int spec_reg, u32 value)
126 * And for many FSL eSDHC controller, the reset value of field
130 if ((spec_reg == SDHCI_CAPABILITIES) && (value & SDHCI_CAN_DO_ADMA1)) {
132 ret = value | SDHCI_CAN_DO_ADMA2;
145 ret = value & 0x000fffff;
146 ret |= (value >> 4) & SDHCI_DATA_LVL_MASK;
147 ret |= (value << 1) & SDHCI_CMD_LVL;
167 ret = value & ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
172 ret = value;
177 int spec_reg, u32 value)
188 ret = value & 0xffff;
190 ret = (value >> shift) & 0xffff;
201 int spec_reg, u32 value)
207 ret = (value >> shift) & 0xff;
215 dma_bits = (value >> 5) & SDHCI_CTRL_DMA_MASK;
224 * esdhc_writel_fixup - Fixup the SD spec register value so that it could be
229 * @value: 8/16/32bit SD spec register value that would be written
230 * @old_value: 32bit eSDHC register value on spec_reg address
237 * Return a fixed up register value
240 int spec_reg, u32 value, u32 old_value)
250 ret = value | SDHCI_INT_BLK_GAP;
252 ret = value;
258 int spec_reg, u16 value, u32 old_value)
268 * command write that is down below. Return old value.
270 pltfm_host->xfer_mode_shadow = value;
273 ret = (value << 16) | pltfm_host->xfer_mode_shadow;
278 ret |= (value << shift);
292 int spec_reg, u8 value, u32 old_value)
318 dma_bits = (value & SDHCI_CTRL_DMA_MASK) << 5;
320 tmp = (value & (~SDHCI_CTRL_DMA_MASK)) |
329 ret = (old_value & (~(0xff << shift))) | (value << shift);
336 u32 value;
339 value = ioread32be(host->ioaddr + ESDHC_CAPABILITIES_1);
341 value = ioread32be(host->ioaddr + reg);
343 ret = esdhc_readl_fixup(host, reg, value);
351 u32 value;
354 value = ioread32(host->ioaddr + ESDHC_CAPABILITIES_1);
356 value = ioread32(host->ioaddr + reg);
358 ret = esdhc_readl_fixup(host, reg, value);
366 u32 value;
369 value = ioread32be(host->ioaddr + base);
370 ret = esdhc_readw_fixup(host, reg, value);
377 u32 value;
380 value = ioread32(host->ioaddr + base);
381 ret = esdhc_readw_fixup(host, reg, value);
388 u32 value;
391 value = ioread32be(host->ioaddr + base);
392 ret = esdhc_readb_fixup(host, reg, value);
399 u32 value;
402 value = ioread32(host->ioaddr + base);
403 ret = esdhc_readb_fixup(host, reg, value);
409 u32 value;
411 value = esdhc_writel_fixup(host, reg, val, 0);
412 iowrite32be(value, host->ioaddr + reg);
417 u32 value;
419 value = esdhc_writel_fixup(host, reg, val, 0);
420 iowrite32(value, host->ioaddr + reg);
428 u32 value;
431 value = ioread32be(host->ioaddr + base);
432 ret = esdhc_writew_fixup(host, reg, val, value);
440 if (!(value & ESDHC_EXTN) && (ret & ESDHC_EXTN) &&
454 u32 value;
457 value = ioread32(host->ioaddr + base);
458 ret = esdhc_writew_fixup(host, reg, val, value);
466 if (!(value & ESDHC_EXTN) && (ret & ESDHC_EXTN) &&
478 u32 value;
481 value = ioread32be(host->ioaddr + base);
482 ret = esdhc_writeb_fixup(host, reg, val, value);
489 u32 value;
492 value = ioread32(host->ioaddr + base);
493 ret = esdhc_writeb_fixup(host, reg, val, value);
533 u32 value;
543 value = sdhci_readl(host, ESDHC_DMA_SYSCTL);
546 value |= ESDHC_DMA_SNOOP;
548 value &= ~ESDHC_DMA_SNOOP;
550 sdhci_writel(host, value, ESDHC_DMA_SYSCTL);
668 /* Fix clock value. */
1073 /* For tuning mode, the sd clock divisor value
1083 * The eSDHC controller takes the data timeout value into account
1088 * Just set the timeout to the maximum value because the core will
1387 * esdhc->peripheral_clock would be assigned with a value
1389 * For some platforms, the clock value got by common clk
1407 * initialize it as 1 or 0 once, to override the different value