Lines Matching refs:val
407 static void esdhc_be_writel(struct sdhci_host *host, u32 val, int reg)
411 value = esdhc_writel_fixup(host, reg, val, 0);
415 static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg)
419 value = esdhc_writel_fixup(host, reg, val, 0);
423 static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg)
432 ret = esdhc_writew_fixup(host, reg, val, value);
449 static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg)
458 ret = esdhc_writew_fixup(host, reg, val, value);
475 static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg)
482 ret = esdhc_writeb_fixup(host, reg, val, value);
486 static void esdhc_le_writeb(struct sdhci_host *host, u8 val, int reg)
493 ret = esdhc_writeb_fixup(host, reg, val, value);
583 u32 val, clk_en;
595 val = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
598 val |= clk_en;
600 val &= ~clk_en;
602 sdhci_writel(host, val, ESDHC_SYSTEM_CONTROL);
626 u32 val;
628 val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
629 val |= ESDHC_FLUSH_ASYNC_FIFO;
630 sdhci_writel(host, val, ESDHC_DMA_SYSCTL);
807 u32 val, bus_width = 0;
824 val = sdhci_readl(host, ESDHC_PROCTL);
825 bus_width = val & ESDHC_CTRL_BUSWIDTH_MASK;
836 val = sdhci_readl(host, ESDHC_PROCTL);
837 val &= ~ESDHC_CTRL_BUSWIDTH_MASK;
838 val |= bus_width;
839 sdhci_writel(host, val, ESDHC_PROCTL);
851 val = sdhci_readl(host, ESDHC_TBCTL);
852 val &= ~ESDHC_TB_EN;
853 sdhci_writel(host, val, ESDHC_TBCTL);
860 val = sdhci_readl(host, ESDHC_DLLCFG1);
861 val &= ~ESDHC_DLL_PD_PULSE_STRETCH_SEL;
862 sdhci_writel(host, val, ESDHC_DLLCFG1);
892 u32 val;
901 val = sdhci_readl(host, ESDHC_PROCTL);
905 val &= ~ESDHC_VOLT_SEL;
906 sdhci_writel(host, val, ESDHC_PROCTL);
919 val |= ESDHC_VOLT_SEL;
920 sdhci_writel(host, val, ESDHC_PROCTL);
929 val |= ESDHC_VOLT_SEL;
930 sdhci_writel(host, val, ESDHC_PROCTL);
958 u32 val;
963 val = sdhci_readl(host, ESDHC_TBCTL);
965 val |= ESDHC_TB_EN;
967 val &= ~ESDHC_TB_EN;
968 sdhci_writel(host, val, ESDHC_TBCTL);
976 u32 val;
979 val = sdhci_readl(host, ESDHC_TBCTL);
980 val &= ~(0xf << 8);
981 val |= 8 << 8;
982 sdhci_writel(host, val, ESDHC_TBCTL);
987 val = sdhci_readl(host, ESDHC_TBCTL);
988 sdhci_writel(host, val, ESDHC_TBCTL);
993 val = sdhci_readl(host, ESDHC_TBSTAT);
994 val = sdhci_readl(host, ESDHC_TBSTAT);
996 *window_end = val & 0xff;
997 *window_start = (val >> 8) & 0xff;
1041 u32 val;
1045 val = ((u32)window_start << ESDHC_WNDW_STRT_PTR_SHIFT) &
1047 val |= window_end & ESDHC_WNDW_END_PTR_MASK;
1048 sdhci_writel(host, val, ESDHC_TBPTR);
1051 val = sdhci_readl(host, ESDHC_TBCTL);
1052 val &= ~ESDHC_TB_MODE_MASK;
1053 val |= ESDHC_TB_MODE_SW;
1054 sdhci_writel(host, val, ESDHC_TBCTL);
1071 u32 val;
1101 val = sdhci_readl(host, ESDHC_TBCTL);
1102 val &= ~ESDHC_TB_MODE_MASK;
1103 val |= ESDHC_TB_MODE_3;
1104 sdhci_writel(host, val, ESDHC_TBCTL);
1166 val = sdhci_readl(host, ESDHC_SDTIMNGCTL);
1167 val |= ESDHC_FLW_CTL_BG;
1168 sdhci_writel(host, val, ESDHC_SDTIMNGCTL);
1177 u32 val;
1184 val = sdhci_readl(host, ESDHC_TBCTL);
1185 if (val & ESDHC_HS400_MODE) {
1186 val = sdhci_readl(host, ESDHC_SDTIMNGCTL);
1187 val &= ~ESDHC_FLW_CTL_BG;
1188 sdhci_writel(host, val, ESDHC_SDTIMNGCTL);
1190 val = sdhci_readl(host, ESDHC_SDCLKCTL);
1191 val &= ~ESDHC_CMD_CLK_CTL;
1192 sdhci_writel(host, val, ESDHC_SDCLKCTL);
1195 val = sdhci_readl(host, ESDHC_TBCTL);
1196 val &= ~ESDHC_HS400_MODE;
1197 sdhci_writel(host, val, ESDHC_TBCTL);
1200 val = sdhci_readl(host, ESDHC_DLLCFG0);
1201 val &= ~(ESDHC_DLL_ENABLE | ESDHC_DLL_FREQ_SEL);
1202 sdhci_writel(host, val, ESDHC_DLLCFG0);
1204 val = sdhci_readl(host, ESDHC_TBCTL);
1205 val &= ~ESDHC_HS400_WNDW_ADJUST;
1206 sdhci_writel(host, val, ESDHC_TBCTL);
1349 u32 val;
1404 val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
1411 val |= ESDHC_PERIPHERAL_CLK_SEL;
1413 val &= ~ESDHC_PERIPHERAL_CLK_SEL;
1414 sdhci_writel(host, val, ESDHC_DMA_SYSCTL);