Lines Matching defs:clock
562 return pltfm_host->clock;
569 unsigned int clock;
572 clock = esdhc->peripheral_clock;
574 clock = pltfm_host->clock;
575 return clock / 256 / 16;
606 * wait clock stable bit which does not exist.
615 pr_err("%s: Internal clock never stabilised.\n",
649 static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
658 if (clock == 0) {
668 /* Fix clock value. */
675 if (clock_fixup == 0 || clock < clock_fixup)
676 clock_fixup = clock;
687 /* Limit clock division for HS400 200MHz clock for quirk. */
689 clock == MMC_HS200_MAX_DTR &&
702 pr_warn("%s: using unsupported clock division.\n",
710 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
711 clock, host->mmc->actual_clock);
713 /* Set clock division into register. */
727 * wait clock stable bit which does not exist.
736 pr_err("%s: Internal clock never stabilised.\n",
745 clock == MMC_HS200_MAX_DTR) {
1073 /* For tuning mode, the sd clock divisor value
1077 if (host->clock > clk)
1098 esdhc_of_set_clock(host, host->clock);
1133 pr_info("%s: Hold on to use fixed sampling clock. Try SW tuning!\n",
1144 /* Retry both HW/SW tuning with reduced clock. */
1153 pr_info("%s: Hold on to use fixed sampling clock. Try tuning with reduced clock!\n",
1388 * which is eSDHC base clock when use periperal clock.
1389 * For some platforms, the clock value got by common clk
1390 * API is peripheral clock while the eSDHC base clock is
1391 * 1/2 peripheral clock.