Lines Matching defs:host
101 static void dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc,
107 sdhci_adma_write_desc(host, desc, addr, len, cmd);
113 sdhci_adma_write_desc(host, desc, addr, tmplen, cmd);
117 sdhci_adma_write_desc(host, desc, addr, len, cmd);
120 static unsigned int dwcmshc_get_max_clock(struct sdhci_host *host)
122 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
125 return sdhci_pltfm_clk_get_max_clock(host);
130 static unsigned int rk35xx_get_max_clock(struct sdhci_host *host)
132 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
140 struct sdhci_host *host = mmc_priv(mmc);
145 * CMD23 argument on dwcmsch host controller.
148 host->flags &= ~SDHCI_AUTO_CMD23;
150 host->flags |= SDHCI_AUTO_CMD23;
160 static void dwcmshc_set_uhs_signaling(struct sdhci_host *host,
163 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
167 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
168 /* Select Bus Speed Mode for host */
185 ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
187 sdhci_writew(host, ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
192 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
199 struct sdhci_host *host = mmc_priv(mmc);
200 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
204 vendor = sdhci_readl(host, reg);
210 sdhci_writel(host, vendor, reg);
213 static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock)
215 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
222 host->mmc->actual_clock = 0;
226 sdhci_set_clock(host, clock);
236 dev_err(mmc_dev(host->mmc), "fail to set clock %d", clock);
238 sdhci_set_clock(host, clock);
242 extra = sdhci_readl(host, reg);
244 sdhci_writel(host, extra, reg);
251 sdhci_writel(host, DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START, DWCMSHC_EMMC_DLL_CTRL);
252 sdhci_writel(host, DLL_RXCLK_ORI_GATE, DWCMSHC_EMMC_DLL_RXCLK);
253 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
254 sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT);
263 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
268 sdhci_writel(host, BIT(1), DWCMSHC_EMMC_DLL_CTRL);
270 sdhci_writel(host, 0x0, DWCMSHC_EMMC_DLL_CTRL);
279 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
285 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL);
286 err = readl_poll_timeout(host->ioaddr + DWCMSHC_EMMC_DLL_STATUS0,
290 dev_err(mmc_dev(host->mmc), "DLL lock timeout!\n");
297 sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
299 if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
300 host->mmc->ios.timing == MMC_TIMING_MMC_HS400)
303 if ((priv->devtype == DWCMSHC_RK3588) && host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
311 sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT);
318 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
323 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
326 static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask)
328 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
338 sdhci_reset(host, mask);
382 static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
387 priv->reset = devm_reset_control_array_get_optional_exclusive(mmc_dev(host->mmc));
390 dev_err(mmc_dev(host->mmc), "failed to get reset control %d\n", err);
397 err = devm_clk_bulk_get_optional(mmc_dev(host->mmc), RK35xx_MAX_CLKS,
400 dev_err(mmc_dev(host->mmc), "failed to get clocks %d\n", err);
406 dev_err(mmc_dev(host->mmc), "failed to enable clocks %d\n", err);
410 if (of_property_read_u8(mmc_dev(host->mmc)->of_node, "rockchip,txclk-tapnum",
415 sdhci_writel(host, 0x0, dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3);
417 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
418 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
423 static void dwcmshc_rk35xx_postinit(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
429 if (host->mmc->f_max <= 52000000) {
430 dev_info(mmc_dev(host->mmc), "Disabling HS200/HS400, frequency too low (%d)\n",
431 host->mmc->f_max);
432 host->mmc->caps2 &= ~(MMC_CAP2_HS200 | MMC_CAP2_HS400);
433 host->mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR);
469 struct sdhci_host *host;
482 host = sdhci_pltfm_init(pdev, pltfm_data,
484 if (IS_ERR(host))
485 return PTR_ERR(host);
493 host->adma_table_cnt += extra;
495 pltfm_host = sdhci_priv(host);
514 err = mmc_of_parse(host->mmc);
521 sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK;
523 host->mmc_host_ops.request = dwcmshc_request;
524 host->mmc_host_ops.hs400_enhanced_strobe = dwcmshc_hs400_enhanced_strobe;
540 err = dwcmshc_rk35xx_init(host, priv);
547 sdhci_enable_v4_mode(host);
550 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
556 err = sdhci_setup_host(host);
561 dwcmshc_rk35xx_postinit(host, priv);
563 err = __sdhci_add_host(host);
572 sdhci_cleanup_host(host);
589 struct sdhci_host *host = platform_get_drvdata(pdev);
590 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
594 sdhci_remove_host(host, 0);
607 struct sdhci_host *host = dev_get_drvdata(dev);
608 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
615 ret = sdhci_suspend_host(host);
632 struct sdhci_host *host = dev_get_drvdata(dev);
633 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
655 ret = sdhci_resume_host(host);
676 static void dwcmshc_enable_card_clk(struct sdhci_host *host)
680 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
683 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
687 static void dwcmshc_disable_card_clk(struct sdhci_host *host)
691 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
694 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
700 struct sdhci_host *host = dev_get_drvdata(dev);
702 dwcmshc_disable_card_clk(host);
709 struct sdhci_host *host = dev_get_drvdata(dev);
711 dwcmshc_enable_card_clk(host);