Lines Matching refs:mhz
1189 u32 mhz = DIV_ROUND_CLOSEST_ULL(clk_get_rate(pltfm_host->clk), 1000000);
1202 sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz);
1739 u32 mhz, node_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 : NODE_SD_1;
1763 mhz = DIV_ROUND_CLOSEST_ULL(clk_get_rate(pltfm_host->clk), 1000000);
1764 if (mhz > 100 && mhz <= 200)
1765 mhz = 200;
1766 else if (mhz > 50 && mhz <= 100)
1767 mhz = 100;
1768 else if (mhz > 25 && mhz <= 50)
1769 mhz = 50;
1771 mhz = 25;
1773 ret = zynqmp_pm_set_sd_config(node_id, SD_CONFIG_BASECLK, mhz);