Lines Matching defs:timing
202 * Some of the Arasan variations might not have timing requirements
400 * Some of the Arasan variations might not have timing
745 switch (host->timing) {
814 switch (host->timing) {
874 switch (host->timing) {
941 switch (host->timing) {
998 switch (host->timing) {
1044 switch (host->timing) {
1112 if (mmc->ios.timing == MMC_TIMING_UHS_DDR50)
1212 clk_data->clk_phase_in[host->timing]);
1214 clk_data->clk_phase_out[host->timing]);
1219 unsigned int timing, const char *prop)
1234 prop, clk_data->clk_phase_in[timing],
1235 clk_data->clk_phase_out[timing]);
1240 clk_data->clk_phase_in[timing] = clk_phase[0];
1241 clk_data->clk_phase_out[timing] = clk_phase[1];