Lines Matching defs:regval
900 u32 regval;
902 regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER);
903 regval |= SDHCI_OTAPDLY_ENABLE;
904 sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
905 regval &= ~SDHCI_ARASAN_OTAPDLY_SEL_MASK;
906 regval |= tap_delay;
907 sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
967 u32 regval;
969 regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER);
970 regval |= SDHCI_ITAPDLY_CHGWIN;
971 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
972 regval |= SDHCI_ITAPDLY_ENABLE;
973 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
974 regval &= ~SDHCI_ARASAN_ITAPDLY_SEL_MASK;
975 regval |= tap_delay;
976 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
977 regval &= ~SDHCI_ITAPDLY_CHGWIN;
978 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
1016 u32 regval;
1018 regval = sdhci_readl(host, PHY_CTRL_REG1);
1019 regval |= PHY_CTRL_OTAPDLY_ENA_MASK;
1020 sdhci_writel(host, regval, PHY_CTRL_REG1);
1021 regval &= ~PHY_CTRL_OTAPDLY_SEL_MASK;
1022 regval |= tap_delay << PHY_CTRL_OTAPDLY_SEL_SHIFT;
1023 sdhci_writel(host, regval, PHY_CTRL_REG1);
1042 u32 regval;
1051 regval = sdhci_readl(host, PHY_CTRL_REG1);
1052 regval &= ~PHY_CTRL_STRB_SEL_MASK;
1053 regval |= VERSAL_NET_PHY_CTRL_STRB90_STRB180_VAL << PHY_CTRL_STRB_SEL_SHIFT;
1054 sdhci_writel(host, regval, PHY_CTRL_REG1);
1064 regval = sdhci_readl(host, PHY_CTRL_REG1);
1065 regval |= PHY_CTRL_ITAP_CHG_WIN_MASK;
1066 sdhci_writel(host, regval, PHY_CTRL_REG1);
1067 regval |= PHY_CTRL_ITAPDLY_ENA_MASK;
1068 sdhci_writel(host, regval, PHY_CTRL_REG1);
1069 regval &= ~PHY_CTRL_ITAPDLY_SEL_MASK;
1070 regval |= tap_delay << PHY_CTRL_ITAPDLY_SEL_SHIFT;
1071 sdhci_writel(host, regval, PHY_CTRL_REG1);
1072 regval &= ~PHY_CTRL_ITAP_CHG_WIN_MASK;
1073 sdhci_writel(host, regval, PHY_CTRL_REG1);