Lines Matching defs:clock
135 * @sdcardclk_ops: The output clock related operations
136 * @sampleclk_ops: The sample clock related operations
146 * @sdcardclk_hw: Struct for the clock we might provide to a PHY.
147 * @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw.
148 * @sampleclk_hw: Struct for the clock we might provide to a PHY.
149 * @sampleclk: Pointer to normal 'struct clock' for sampleclk_hw.
153 * @clk_of_data: Platform specific runtime clock data storage pointer
170 * @clk_ahb: Pointer to the AHB clock
199 * internal clock even when the clock isn't stable */
273 static void sdhci_arasan_phy_dll_set_freq(struct sdhci_host *host, int clock)
277 freq = DIV_ROUND_CLOSEST(clock, 1000000);
347 static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock)
355 if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) {
357 * If PHY off, set clock to max speed and power PHY on.
360 * when changing the clock the PHY doesn't like to be
363 * clock is off.
381 * sdhci_set_clock() will set the real clock.
383 } else if (clock > PHY_CLK_TOO_SLOW_HZ) {
385 * At higher clock speeds the PHY is fine being power
387 * changing clock speeds.
404 if (clock == DEFAULT_SPEED_MAX_DTR)
405 clock = (DEFAULT_SPEED_MAX_DTR * 19) / 25;
409 if (clk_data->set_clk_delays && clock > PHY_CLK_TOO_SLOW_HZ)
412 if (sdhci_arasan->internal_phy_reg && clock >= MIN_PHY_CLK_HZ) {
416 sdhci_arasan_phy_dll_set_freq(host, clock);
422 sdhci_set_clock(host, clock);
424 if (sdhci_arasan->internal_phy_reg && clock >= MIN_PHY_CLK_HZ)
430 * after enabling the clock even though the clock is not
431 * stable. Trying to use a clock without waiting here results
630 dev_err(dev, "Cannot enable AHB clock.\n");
636 dev_err(dev, "Cannot enable SD clock.\n");
666 * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate
668 * @hw: Pointer to the hardware clock structure.
671 * Return the current actual rate of the SD card clock. This can be used
674 * Return: The card clock rate.
693 * sdhci_arasan_sampleclk_recalc_rate - Return the sampling clock rate
695 * @hw: Pointer to the hardware clock structure.
698 * Return the current actual rate of the sampling clock. This can be used
701 * Return: The sample clock rate.
722 * @hw: Pointer to the hardware clock structure.
723 * @degrees: The clock phase shift between 0 - 359.
751 /* For 50MHz clock, 30 Taps are available */
755 /* For 100MHz clock, 15 Taps are available */
760 /* For 200MHz clock, 8 Taps are available */
788 * @hw: Pointer to the hardware clock structure.
789 * @degrees: The clock phase shift between 0 - 359.
820 /* For 50MHz clock, 120 Taps are available */
824 /* For 100MHz clock, 60 Taps are available */
829 /* For 200MHz clock, 30 Taps are available */
854 * @hw: Pointer to the hardware clock structure.
855 * @degrees: The clock phase shift between 0 - 359.
880 /* For 50MHz clock, 30 Taps are available */
884 /* For 100MHz clock, 15 Taps are available */
889 /* For 200MHz clock, 8 Taps are available */
921 * @hw: Pointer to the hardware clock structure.
922 * @degrees: The clock phase shift between 0 - 359.
947 /* For 50MHz clock, 120 Taps are available */
951 /* For 100MHz clock, 60 Taps are available */
956 /* For 200MHz clock, 30 Taps are available */
1005 /* For 200MHz clock, 32 Taps are available */
1132 * The corecfg_clockmultiplier is supposed to contain clock multiplier
1133 * value of programmable clock generator.
1180 * to achieve lower clock rates. That means that this function is called once
1233 dev_dbg(dev, "Using predefined clock phase for %s = %d %d\n",
1531 * @clk_xin: Pointer to the functional clock
1534 * Some PHY devices need to know what the actual card clock is. In order for
1535 * them to find out, we'll provide a clock through the common clock framework
1551 ret = of_property_read_string_index(np, "clock-output-names", 0,
1554 dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
1574 dev_err(dev, "Failed to add sdcard clock provider\n");
1583 * @clk_xin: Pointer to the functional clock
1586 * Some PHY devices need to know what the actual card clock is. In order for
1587 * them to find out, we'll provide a clock through the common clock framework
1603 ret = of_property_read_string_index(np, "clock-output-names", 1,
1606 dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
1626 dev_err(dev, "Failed to add sample clock provider\n");
1643 if (!of_property_present(np, "#clock-cells"))
1687 * @clk_xin: Pointer to the functional clock
1690 * Some PHY devices need to know what the actual card clock is. In order for
1691 * them to find out, we'll provide a clock through the common clock framework
1694 * Note: without seriously re-architecting SDHCI's clock code and testing on
1695 * all platforms, there's no way to create a totally beautiful clock here
1696 * with all clock ops implemented. Instead, we'll just create a clock that can
1697 * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock
1712 /* Providing a clock to the PHY is optional; no error if missing */
1713 if (of_property_read_u32(np, "#clock-cells", &num_clks) < 0)
1881 "clk_ahb clock not found.\n");
1887 ret = dev_err_probe(dev, PTR_ERR(clk_xin), "clk_xin clock not found.\n");
1893 dev_err(dev, "Unable to enable AHB clock.\n");
1897 /* If clock-frequency property is set, use the provided value */
1898 if (pltfm_host->clock &&
1899 pltfm_host->clock != clk_get_rate(clk_xin)) {
1900 ret = clk_set_rate(clk_xin, pltfm_host->clock);
1902 dev_err(&pdev->dev, "Failed to set SD clock rate\n");
1909 dev_err(dev, "Unable to enable SD clock.\n");
1922 if (of_property_read_bool(np, "xlnx,int-clock-stable-broken"))