Lines Matching defs:clk_xin
669 * @parent_rate: The parent rate (should be rate of clk_xin).
696 * @parent_rate: The parent rate (should be rate of clk_xin).
1171 * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin. This
1179 * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider
1531 * @clk_xin: Pointer to the functional clock
1542 struct clk *clk_xin,
1558 parent_clk_name = __clk_get_name(clk_xin);
1583 * @clk_xin: Pointer to the functional clock
1594 struct clk *clk_xin,
1610 parent_clk_name = __clk_get_name(clk_xin);
1687 * @clk_xin: Pointer to the functional clock
1705 struct clk *clk_xin,
1716 ret = sdhci_arasan_register_sdcardclk(sdhci_arasan, clk_xin, dev);
1721 ret = sdhci_arasan_register_sampleclk(sdhci_arasan, clk_xin,
1838 struct clk *clk_xin;
1885 clk_xin = devm_clk_get(dev, "clk_xin");
1886 if (IS_ERR(clk_xin)) {
1887 ret = dev_err_probe(dev, PTR_ERR(clk_xin), "clk_xin clock not found.\n");
1899 pltfm_host->clock != clk_get_rate(clk_xin)) {
1900 ret = clk_set_rate(clk_xin, pltfm_host->clock);
1907 ret = clk_prepare_enable(clk_xin);
1925 pltfm_host->clk = clk_xin;
1941 ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, dev);
2011 clk_disable_unprepare(clk_xin);
2025 struct clk *clk_xin = pltfm_host->clk;
2037 clk_disable_unprepare(clk_xin);