Lines Matching refs:phase
421 static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
434 if (phase > 0xf)
450 * Write the selected DLL clock output phase (0 ... 15)
455 config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT;
474 dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n",
475 mmc_hostname(mmc), phase);
488 * selected DLL clock output phase.
515 /* check if next phase in phase_table is consecutive or not */
525 /* Check if phase-0 is present in first valid window? */
545 /* number of phases in raw where phase 0 is present */
547 /* number of phases in raw where phase 15 is present */
552 * If there are more than 1 phase windows then total
586 dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n",
914 * tuning block and restore the saved tuning phase.
920 /* Set the selected phase in delay line hw block */
1094 * tuning block and restore the saved tuning phase.
1101 /* Set the selected phase in delay line hw block */
1190 u8 phase, tuned_phases[16], tuned_phase_cnt = 0;
1228 phase = 0;
1230 /* Set the phase in delay line hw block */
1231 rc = msm_config_cm_dll_phase(host, phase);
1238 tuned_phases[tuned_phase_cnt++] = phase;
1239 dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
1240 mmc_hostname(mmc), phase);
1242 } while (++phase < ARRAY_SIZE(tuned_phases));
1251 * we get a good phase. Better to try a few times.
1266 phase = rc;
1269 * Finally set the selected phase in delay
1272 rc = msm_config_cm_dll_phase(host, phase);
1275 msm_host->saved_tuning_phase = phase;
1276 dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n",
1277 mmc_hostname(mmc), phase);