Lines Matching refs:msm_offset
399 const struct sdhci_msm_offset *msm_offset =
404 msm_offset->core_dll_config) & CORE_CK_OUT_EN);
415 msm_offset->core_dll_config) & CORE_CK_OUT_EN);
431 const struct sdhci_msm_offset *msm_offset =
439 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
442 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
453 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
456 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
458 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
460 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
467 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
470 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
596 const struct sdhci_msm_offset *msm_offset =
617 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
620 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
632 const struct sdhci_msm_offset *msm_offset =
645 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
647 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
651 host->ioaddr + msm_offset->core_dll_config);
655 msm_offset->core_dll_config);
658 msm_offset->core_dll_config);
661 msm_offset->core_dll_config_2);
664 msm_offset->core_dll_config_2);
668 msm_offset->core_dll_config);
671 msm_offset->core_dll_config);
674 msm_offset->core_dll_config);
677 msm_offset->core_dll_config);
687 msm_offset->core_dll_config_2);
697 msm_offset->core_dll_config_2);
702 msm_offset->core_dll_config_2);
708 msm_offset->core_dll_config);
711 msm_offset->core_dll_config);
714 msm_offset->core_dll_config);
717 msm_offset->core_dll_config);
723 msm_offset->core_dll_config_2);
726 msm_offset->core_dll_config_2);
737 msm_offset->core_dll_usr_ctl);
740 msm_offset->core_dll_config_3);
747 msm_offset->core_dll_config_3);
751 msm_offset->core_dll_config);
754 msm_offset->core_dll_config);
757 msm_offset->core_dll_config);
760 msm_offset->core_dll_config);
763 while (!(readl_relaxed(host->ioaddr + msm_offset->core_dll_status) &
784 const struct sdhci_msm_offset *msm_offset =
789 msm_offset->core_vendor_spec3);
792 msm_offset->core_vendor_spec3);
795 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
798 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
807 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
810 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
826 const struct sdhci_msm_offset *msm_offset =
830 config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
834 writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
842 msm_offset->core_vendor_spec);
846 msm_offset->core_vendor_spec);
855 msm_offset->core_dll_status,
907 const struct sdhci_msm_offset *msm_offset =
925 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
927 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
929 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
931 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
941 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
943 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
995 config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
997 writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
1011 const struct sdhci_msm_offset *msm_offset =
1024 ddr_cfg_offset = msm_offset->core_ddr_config;
1026 ddr_cfg_offset = msm_offset->core_ddr_config_old;
1031 msm_offset->core_ddr_200_cfg);
1034 msm_offset->core_ddr_200_cfg);
1037 config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2);
1039 writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config_2);
1042 msm_offset->core_dll_status,
1063 msm_offset->core_vendor_spec3);
1066 msm_offset->core_vendor_spec3);
1087 const struct sdhci_msm_offset *msm_offset =
1107 msm_offset->core_dll_config);
1110 msm_offset->core_dll_config);
1167 const struct sdhci_msm_offset *msm_offset = sdhci_priv_msm_offset(host);
1169 msm_offset->core_dll_config);
1182 msm_offset->core_dll_config);
1324 const struct sdhci_msm_offset *msm_offset =
1367 msm_offset->core_dll_config);
1370 msm_offset->core_dll_config);
1373 msm_offset->core_dll_config);
1376 msm_offset->core_dll_config);
1521 const struct sdhci_msm_offset *msm_offset =
1536 msm_offset->core_generics);
1584 const struct sdhci_msm_offset *msm_offset =
1589 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_status),
1590 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_mask),
1591 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_ctl));
1603 const struct sdhci_msm_offset *msm_offset = msm_host->offset;
1606 msm_offset->core_pwrctl_status);
1610 msm_offset->core_pwrctl_clear);
1620 msm_offset->core_pwrctl_status)) {
1629 msm_offset->core_pwrctl_clear);
1685 msm_offset->core_pwrctl_ctl);
1705 msm_offset->core_vendor_spec);
1717 msm_offset->core_vendor_spec);
2147 const struct sdhci_msm_offset *msm_offset = msm_host->offset;
2168 msm_offset->core_vendor_spec);
2177 host->ioaddr + msm_offset->core_vendor_spec);
2256 const struct sdhci_msm_offset *msm_offset = msm_host->offset;
2262 readl_relaxed(host->ioaddr + msm_offset->core_dll_status),
2263 readl_relaxed(host->ioaddr + msm_offset->core_dll_config),
2264 readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2));
2267 readl_relaxed(host->ioaddr + msm_offset->core_dll_config_3),
2268 readl_relaxed(host->ioaddr + msm_offset->core_dll_usr_ctl),
2269 readl_relaxed(host->ioaddr + msm_offset->core_ddr_config));
2272 readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec),
2274 msm_offset->core_vendor_spec_func2),
2275 readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec3));
2411 const struct sdhci_msm_offset *msm_offset;
2440 msm_offset = msm_host->offset;
2537 host->ioaddr + msm_offset->core_vendor_spec);
2542 msm_offset->core_hc_mode);
2544 msm_offset->core_hc_mode);
2547 msm_offset->core_hc_mode);
2556 msm_offset->core_mci_version);
2581 msm_offset->core_vendor_spec_capabilities0);
2619 msm_offset->core_pwrctl_mask);