Lines Matching refs:msm_host
140 #define msm_host_readl(msm_host, host, offset) \
141 msm_host->var_ops->msm_readl_relaxed(host, offset)
143 #define msm_host_writel(msm_host, val, host, offset) \
144 msm_host->var_ops->msm_writel_relaxed(val, host, offset)
298 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
300 return msm_host->offset;
311 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
313 return readl_relaxed(msm_host->core_mem + offset);
326 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
328 writel_relaxed(val, msm_host->core_mem + offset);
358 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
360 struct clk *core_clk = msm_host->bulk_clks[0].clk;
387 msm_host->clk_rate = desired_rate;
628 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
633 msm_host->offset;
635 if (msm_host->use_14lpp_dll_reset && !IS_ERR_OR_NULL(msm_host->xo_clk))
636 xo_clk = clk_get_rate(msm_host->xo_clk);
649 if (msm_host->dll_config)
650 writel_relaxed(msm_host->dll_config,
653 if (msm_host->use_14lpp_dll_reset) {
679 if (!msm_host->dll_config)
682 if (msm_host->use_14lpp_dll_reset &&
683 !IS_ERR_OR_NULL(msm_host->xo_clk)) {
719 if (msm_host->use_14lpp_dll_reset) {
720 if (!msm_host->dll_config)
733 if (msm_host->uses_tassadar_dll) {
742 if (msm_host->clk_rate < 150000000)
782 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
785 msm_host->offset;
787 if (!msm_host->use_cdclp533) {
822 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
827 msm_host->offset;
839 if ((msm_host->tuning_done || ios.enhanced_strobe) &&
840 !msm_host->calibration_done) {
848 if (!msm_host->clk_rate && !msm_host->use_cdclp533) {
904 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
908 msm_host->offset;
921 ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
1010 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1023 if (msm_host->updated_ddr_cfg)
1027 writel_relaxed(msm_host->ddr_config, host->ioaddr + ddr_cfg_offset);
1061 if (!msm_host->use_14lpp_dll_reset) {
1083 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1088 msm_host->offset;
1103 msm_host->saved_tuning_phase);
1113 if (msm_host->use_cdclp533)
1144 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1160 ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
1194 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1197 msm_host->use_cdr = false;
1203 msm_host->use_cdr = true;
1209 msm_host->tuning_done = 0;
1275 msm_host->saved_tuning_phase = phase;
1288 msm_host->tuning_done = true;
1301 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1305 (msm_host->tuning_done || ios->enhanced_strobe) &&
1306 !msm_host->calibration_done) {
1309 msm_host->calibration_done = true;
1321 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1325 msm_host->offset;
1382 msm_host->calibration_done = false;
1393 static int sdhci_msm_set_pincfg(struct sdhci_msm_host *msm_host, bool level)
1395 struct platform_device *pdev = msm_host->pdev;
1414 static int msm_toggle_vqmmc(struct sdhci_msm_host *msm_host,
1420 if (msm_host->vqmmc_enabled == level)
1425 if (msm_host->caps_0 & CORE_3_0V_SUPPORT)
1427 else if (msm_host->caps_0 & CORE_1_8V_SUPPORT)
1430 if (msm_host->caps_0 & CORE_VOLT_SUPPORT) {
1447 msm_host->vqmmc_enabled = level;
1452 static int msm_config_vqmmc_mode(struct sdhci_msm_host *msm_host,
1465 static int sdhci_msm_set_vqmmc(struct sdhci_msm_host *msm_host,
1488 ret = msm_config_vqmmc_mode(msm_host, mmc, level);
1490 ret = msm_toggle_vqmmc(msm_host, mmc, level);
1495 static inline void sdhci_msm_init_pwr_irq_wait(struct sdhci_msm_host *msm_host)
1497 init_waitqueue_head(&msm_host->pwr_irq_wait);
1501 struct sdhci_msm_host *msm_host)
1503 wake_up(&msm_host->pwr_irq_wait);
1518 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1522 msm_host->offset;
1526 msm_host->curr_pwr_state, msm_host->curr_io_level);
1534 if (!msm_host->mci_removed)
1535 val = msm_host_readl(msm_host, host,
1559 if ((req_type & msm_host->curr_pwr_state) ||
1560 (req_type & msm_host->curr_io_level))
1569 if (!wait_event_timeout(msm_host->pwr_irq_wait,
1570 msm_host->pwr_irq_flag,
1572 dev_warn(&msm_host->pdev->dev,
1583 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1585 msm_host->offset;
1589 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_status),
1590 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_mask),
1591 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_ctl));
1597 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1603 const struct sdhci_msm_offset *msm_offset = msm_host->offset;
1605 irq_status = msm_host_readl(msm_host, host,
1609 msm_host_writel(msm_host, irq_status, host,
1619 while (irq_status & msm_host_readl(msm_host, host,
1628 msm_host_writel(msm_host, irq_status, host,
1647 ret = sdhci_msm_set_vqmmc(msm_host, mmc,
1650 ret = sdhci_msm_set_pincfg(msm_host,
1684 msm_host_writel(msm_host, irq_ack, host,
1691 if (msm_host->caps_0 & CORE_VOLT_SUPPORT) {
1709 (msm_host->caps_0 & CORE_3_0V_SUPPORT))
1712 (msm_host->caps_0 & CORE_1_8V_SUPPORT))
1721 msm_host->curr_pwr_state = pwr_state;
1723 msm_host->curr_io_level = io_level;
1726 mmc_hostname(msm_host->mmc), __func__, irq, irq_status,
1734 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1737 msm_host->pwr_irq_flag = 1;
1738 sdhci_msm_complete_pwr_irq_wait(msm_host);
1747 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1748 struct clk *core_clk = msm_host->bulk_clks[0].clk;
1788 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1791 host->mmc->actual_clock = msm_host->clk_rate = 0;
1810 static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host,
1813 struct mmc_host *mmc = msm_host->mmc;
1829 msm_host->ice = ice;
1835 static void sdhci_msm_ice_enable(struct sdhci_msm_host *msm_host)
1837 if (msm_host->mmc->caps2 & MMC_CAP2_CRYPTO)
1838 qcom_ice_enable(msm_host->ice);
1841 static __maybe_unused int sdhci_msm_ice_resume(struct sdhci_msm_host *msm_host)
1843 if (msm_host->mmc->caps2 & MMC_CAP2_CRYPTO)
1844 return qcom_ice_resume(msm_host->ice);
1849 static __maybe_unused int sdhci_msm_ice_suspend(struct sdhci_msm_host *msm_host)
1851 if (msm_host->mmc->caps2 & MMC_CAP2_CRYPTO)
1852 return qcom_ice_suspend(msm_host->ice);
1867 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1877 return qcom_ice_program_key(msm_host->ice,
1883 return qcom_ice_evict_key(msm_host->ice, slot);
1888 static inline int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host,
1894 static inline void sdhci_msm_ice_enable(struct sdhci_msm_host *msm_host)
1899 sdhci_msm_ice_resume(struct sdhci_msm_host *msm_host)
1905 sdhci_msm_ice_suspend(struct sdhci_msm_host *msm_host)
1933 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1936 sdhci_msm_ice_enable(msm_host);
1999 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2023 msm_host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
2028 ret = sdhci_msm_ice_init(msm_host, cq_host);
2076 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2092 msm_host->transfer_mode = val;
2095 if (!msm_host->use_cdr)
2097 if ((msm_host->transfer_mode & SDHCI_TRNS_READ) &&
2106 msm_host->pwr_irq_flag = 0;
2141 static void sdhci_msm_set_regulator_caps(struct sdhci_msm_host *msm_host)
2143 struct mmc_host *mmc = msm_host->mmc;
2147 const struct sdhci_msm_offset *msm_offset = msm_host->offset;
2165 u32 io_level = msm_host->curr_io_level;
2179 msm_host->caps_0 |= caps;
2183 static int sdhci_msm_register_vreg(struct sdhci_msm_host *msm_host)
2187 ret = mmc_regulator_get_supply(msm_host->mmc);
2191 sdhci_msm_set_regulator_caps(msm_host);
2255 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2256 const struct sdhci_msm_offset *msm_offset = msm_host->offset;
2351 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2354 &msm_host->ddr_config))
2355 msm_host->ddr_config = DDR_CONFIG_POR_VAL;
2357 of_property_read_u32(node, "qcom,dll-config", &msm_host->dll_config);
2405 struct sdhci_msm_host *msm_host;
2415 host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host));
2421 msm_host = sdhci_pltfm_priv(pltfm_host);
2422 msm_host->mmc = host->mmc;
2423 msm_host->pdev = pdev;
2435 msm_host->mci_removed = var_info->mci_removed;
2436 msm_host->restore_dll_config = var_info->restore_dll_config;
2437 msm_host->var_ops = var_info->var_ops;
2438 msm_host->offset = var_info->offset;
2440 msm_offset = msm_host->offset;
2445 msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;
2452 msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
2453 if (!IS_ERR(msm_host->bus_clk)) {
2455 ret = clk_set_rate(msm_host->bus_clk, INT_MAX);
2458 ret = clk_prepare_enable(msm_host->bus_clk);
2470 msm_host->bulk_clks[1].clk = clk;
2479 msm_host->bulk_clks[0].clk = clk;
2505 msm_host->bulk_clks[2].clk = clk;
2510 msm_host->bulk_clks[3].clk = clk;
2512 ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
2513 msm_host->bulk_clks);
2521 msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo");
2522 if (IS_ERR(msm_host->xo_clk)) {
2523 ret = PTR_ERR(msm_host->xo_clk);
2527 if (!msm_host->mci_removed) {
2528 msm_host->core_mem = devm_platform_ioremap_resource(pdev, 1);
2529 if (IS_ERR(msm_host->core_mem)) {
2530 ret = PTR_ERR(msm_host->core_mem);
2539 if (!msm_host->mci_removed) {
2541 msm_host_writel(msm_host, HC_MODE_EN, host,
2543 config = msm_host_readl(msm_host, host,
2546 msm_host_writel(msm_host, config, host,
2555 core_version = msm_host_readl(msm_host, host,
2564 msm_host->use_14lpp_dll_reset = true;
2571 msm_host->use_cdclp533 = true;
2585 msm_host->updated_ddr_cfg = true;
2588 msm_host->uses_tassadar_dll = true;
2590 ret = sdhci_msm_register_vreg(msm_host);
2610 msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq");
2611 if (msm_host->pwr_irq < 0) {
2612 ret = msm_host->pwr_irq;
2616 sdhci_msm_init_pwr_irq_wait(msm_host);
2618 msm_host_writel(msm_host, INT_MASK, host,
2621 ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL,
2629 msm_host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY;
2661 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
2662 msm_host->bulk_clks);
2664 if (!IS_ERR(msm_host->bus_clk))
2665 clk_disable_unprepare(msm_host->bus_clk);
2675 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2685 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
2686 msm_host->bulk_clks);
2687 if (!IS_ERR(msm_host->bus_clk))
2688 clk_disable_unprepare(msm_host->bus_clk);
2696 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2700 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
2701 msm_host->bulk_clks);
2703 return sdhci_msm_ice_suspend(msm_host);
2710 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2713 ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
2714 msm_host->bulk_clks);
2721 if (msm_host->restore_dll_config && msm_host->clk_rate) {
2727 dev_pm_opp_set_rate(dev, msm_host->clk_rate);
2729 return sdhci_msm_ice_resume(msm_host);