Lines Matching defs:mode
168 /* The IP supports HS200 mode */
170 /* The IP supports HS400 mode */
174 * uSDHC: At 1.8V due to the I/O timing limit, for SDR mode, SD card
175 * clock can't exceed 150MHz, for DDR mode, SD card clock can't exceed 45MHz.
178 /* The IP supports HS400ES mode */
184 /* The IP state got lost in low power mode */
189 * The IP do not support the ACMD23 feature completely when use ADMA mode.
190 * In ADMA mode, it only use the 16 bit block count of the register 0x4
191 * (BLOCK_ATT) as the CMD23's argument for ACMD23 mode, which means it will
195 * imx6qpdl/imx6sx/imx6sl/imx7d has this limitation only for ADMA mode, SDMA
196 * do not has this limitation. so when these SoC use ADMA mode, it need to
763 * Since already disable DMA mode, so also need
849 /* DMA mode bits are shifted */
1102 * DDR50, normally does not require tuning for DDR50 mode.
1241 * in HS400 mode. The frequency of this signal follows the frequency of
1295 /* disable ddr mode and disable HS400 mode */
1535 u16 mode;
1559 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
1561 mode |= SDHCI_TRNS_DMA;
1563 mode |= SDHCI_TRNS_BLK_CNT_EN;
1564 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1875 /* re-initialize hw state in case it's lost in low power mode */