Lines Matching refs:pcr
27 struct rtsx_pcr *pcr;
57 rtsx_pci_write_register(host->pcr, CARD_STOP,
74 rtsx_pci_read_register(host->pcr, start + i + j,
92 return rtsx_pci_readl(host->pcr, RTSX_BIPR) & SD_EXIST;
95 static void sd_cmd_set_sd_cmd(struct rtsx_pcr *pcr, struct mmc_command *cmd)
97 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF,
99 rtsx_pci_write_be32(pcr, SD_CMD1, cmd->arg);
102 static void sd_cmd_set_data_len(struct rtsx_pcr *pcr, u16 blocks, u16 blksz)
104 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, blocks);
105 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, blocks >> 8);
106 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, blksz);
107 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, blksz >> 8);
150 struct rtsx_pcr *pcr = host->pcr;
163 count = rtsx_pci_dma_map_sg(pcr, data->sg, data->sg_len, read);
201 struct rtsx_pcr *pcr = host->pcr;
205 rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, read);
212 struct rtsx_pcr *pcr = host->pcr;
236 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
244 rtsx_pci_init_cmd(pcr);
245 sd_cmd_set_sd_cmd(pcr, cmd);
246 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
247 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
249 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
251 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
258 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
262 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
265 rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0);
267 err = rtsx_pci_send_cmd(pcr, timeout);
282 ptr = rtsx_pci_get_cmd_data(pcr) + 1;
323 rtsx_pci_write_register(pcr, SD_BUS_STAT,
330 struct rtsx_pcr *pcr = host->pcr;
345 rtsx_pci_init_cmd(pcr);
346 sd_cmd_set_sd_cmd(pcr, cmd);
347 sd_cmd_set_data_len(pcr, 1, byte_cnt);
348 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
352 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
355 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
357 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
360 err = rtsx_pci_send_cmd(pcr, timeout);
369 err = rtsx_pci_read_ppbuf(pcr, buf, buf_len);
384 struct rtsx_pcr *pcr = host->pcr;
398 err = rtsx_pci_write_ppbuf(pcr, buf, buf_len);
406 rtsx_pci_init_cmd(pcr);
407 sd_cmd_set_data_len(pcr, 1, byte_cnt);
408 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
411 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
413 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
416 err = rtsx_pci_send_cmd(pcr, timeout);
430 struct rtsx_pcr *pcr = host->pcr;
451 rtsx_pci_init_cmd(pcr);
452 sd_cmd_set_sd_cmd(pcr, cmd);
453 sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
454 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
456 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
458 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
460 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
462 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
463 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
466 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
468 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2 | resp_type);
469 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
471 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
473 rtsx_pci_send_cmd_no_wait(pcr);
475 err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 1, 10000);
488 struct rtsx_pcr *pcr = host->pcr;
511 rtsx_pci_init_cmd(pcr);
512 sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
513 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
515 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
517 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
519 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
521 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
522 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
525 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
527 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2);
528 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
530 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
532 rtsx_pci_send_cmd_no_wait(pcr);
533 err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 0, 10000);
544 rtsx_pci_write_register(host->pcr, SD_CFG1,
550 rtsx_pci_write_register(host->pcr, SD_CFG1,
618 struct rtsx_pcr *pcr = host->pcr;
623 rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
626 rtsx_pci_write_register(pcr, SD_VPRX_CTL,
630 rtsx_pci_write_register(pcr, SD_VPTX_CTL,
633 rtsx_pci_write_register(pcr, SD_VP_CTL, PHASE_NOT_RESET, 0);
634 rtsx_pci_write_register(pcr, SD_VP_CTL, PHASE_NOT_RESET,
636 rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, 0);
637 rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
692 rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val);
705 struct rtsx_pcr *pcr = host->pcr;
709 rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
718 rtsx_pci_write_register(pcr, SD_CFG3,
723 rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
800 struct rtsx_pcr *pcr = host->pcr;
815 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
821 mutex_lock(&pcr->pcr_mutex);
823 rtsx_pci_start_run(pcr);
825 rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth,
827 rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL);
828 rtsx_pci_write_register(pcr, CARD_SHARE_MODE,
858 mutex_unlock(&pcr->pcr_mutex);
899 err = rtsx_pci_write_register(host->pcr, SD_CFG1,
907 struct rtsx_pcr *pcr = host->pcr;
917 rtsx_pci_write_register(pcr, SD_BUS_STAT, SD_CLK_TOGGLE_EN, 0);
923 rtsx_pci_init_cmd(pcr);
924 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL);
925 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE,
927 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN,
929 err = rtsx_pci_send_cmd(pcr, 100);
933 err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD);
937 err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD);
943 err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
948 rtsx_pci_write_register(pcr, SD_BUS_STAT, SD_CLK_TOGGLE_EN, SD_CLK_TOGGLE_EN);
950 if (PCI_PID(pcr) == PID_5261) {
955 rtsx_pci_read_register(pcr, RTS5261_FW_CFG_INFO0, &test_mode);
960 if (pcr->extra_caps & EXTRA_CAPS_SD_EXPRESS)
967 val = rtsx_pci_readl(pcr, RTSX_BIPR);
969 pcr->extra_caps &= ~EXTRA_CAPS_SD_EXPRESS;
981 struct rtsx_pcr *pcr = host->pcr;
986 rtsx_pci_init_cmd(pcr);
988 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
989 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
991 err = rtsx_pci_send_cmd(pcr, 100);
995 err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
999 return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
1017 struct rtsx_pcr *pcr = host->pcr;
1020 rtsx_pci_init_cmd(pcr);
1025 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1028 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1030 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1032 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1037 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1040 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1042 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1044 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1045 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1047 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1054 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1056 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1058 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1060 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1061 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1063 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1068 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1070 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1072 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1074 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1075 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1077 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1082 err = rtsx_pci_send_cmd(pcr, 100);
1090 struct rtsx_pcr *pcr = host->pcr;
1095 if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD))
1098 mutex_lock(&pcr->pcr_mutex);
1100 rtsx_pci_start_run(pcr);
1129 rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth,
1132 mutex_unlock(&pcr->pcr_mutex);
1138 struct rtsx_pcr *pcr = host->pcr;
1145 mutex_lock(&pcr->pcr_mutex);
1147 rtsx_pci_start_run(pcr);
1150 val = rtsx_pci_readl(pcr, RTSX_BIPR);
1155 mutex_unlock(&pcr->pcr_mutex);
1163 struct rtsx_pcr *pcr = host->pcr;
1170 mutex_lock(&pcr->pcr_mutex);
1172 rtsx_pci_start_run(pcr);
1175 val = rtsx_pci_card_exist(pcr);
1180 mutex_unlock(&pcr->pcr_mutex);
1187 struct rtsx_pcr *pcr = host->pcr;
1201 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1210 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1220 struct rtsx_pcr *pcr = host->pcr;
1228 err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
1238 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1249 rtsx_pci_write_register(pcr, SD_BUS_STAT,
1251 rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0);
1261 struct rtsx_pcr *pcr = host->pcr;
1271 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1275 mutex_lock(&pcr->pcr_mutex);
1277 rtsx_pci_start_run(pcr);
1290 err = rtsx_pci_switch_output_voltage(pcr, voltage);
1302 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1305 mutex_unlock(&pcr->pcr_mutex);
1313 struct rtsx_pcr *pcr = host->pcr;
1319 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1323 mutex_lock(&pcr->pcr_mutex);
1325 rtsx_pci_start_run(pcr);
1330 err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false);
1334 err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false);
1338 err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false);
1353 err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true);
1356 mutex_unlock(&pcr->pcr_mutex);
1365 struct rtsx_pcr *pcr = host->pcr;
1370 rtsx_pci_write_register(pcr, 0xFF01, 0xFF, relink_time);
1371 rtsx_pci_write_register(pcr, 0xFF02, 0xFF, relink_time >> 8);
1372 rtsx_pci_write_register(pcr, 0xFF03, 0x01, relink_time >> 16);
1374 rtsx_pci_write_register(pcr, PETXCFG, 0x80, 0x80);
1375 rtsx_pci_write_register(pcr, LDO_VCC_CFG0,
1377 pcr->option.sd_800mA_ocp_thd);
1379 if (pcr->ops->disable_auto_blink)
1380 pcr->ops->disable_auto_blink(pcr);
1383 pcr->hw_param.interrupt_en &= ~(SD_INT_EN);
1384 rtsx_pci_writel(pcr, RTSX_BIER, pcr->hw_param.interrupt_en);
1386 rtsx_pci_write_register(pcr, RTS5260_AUTOLOAD_CFG4,
1388 rtsx_pci_write_register(pcr, RTS5261_FW_CFG0,
1390 rtsx_pci_write_register(pcr, RTS5261_FW_CFG1,
1392 rtsx_pci_write_register(pcr, RTS5261_FW_CFG1,
1415 struct rtsx_pcr *pcr = host->pcr;
1417 dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps);
1419 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50)
1421 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
1423 if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50)
1425 if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR)
1427 if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT)
1429 if (pcr->extra_caps & EXTRA_CAPS_NO_MMC)
1431 if (pcr->extra_caps & EXTRA_CAPS_SD_EXPRESS)
1438 struct rtsx_pcr *pcr = host->pcr;
1446 if (pcr->rtd3_en)
1475 struct rtsx_pcr *pcr;
1482 pcr = handle->pcr;
1483 if (!pcr)
1493 host->pcr = pcr;
1501 pcr->slots[RTSX_SD_CARD].p_dev = pdev;
1502 pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event;
1529 struct rtsx_pcr *pcr;
1532 pcr = host->pcr;
1533 pcr->slots[RTSX_SD_CARD].p_dev = NULL;
1534 pcr->slots[RTSX_SD_CARD].card_event = NULL;
1545 rtsx_pci_complete_unfinished_transfer(pcr);