Lines Matching refs:base
101 void __iomem *base;
142 state = readl(owl_host->base + OWL_REG_SD_STATE);
144 state = readl(owl_host->base + OWL_REG_SD_STATE);
146 writel(state, owl_host->base + OWL_REG_SD_STATE);
223 mode |= (readl(owl_host->base + OWL_REG_SD_CTL) & (0xff << 16));
226 writel(cmd->arg, owl_host->base + OWL_REG_SD_ARG);
227 writel(cmd->opcode, owl_host->base + OWL_REG_SD_CMD);
240 writel(mode, owl_host->base + OWL_REG_SD_CTL);
254 state = readl(owl_host->base + OWL_REG_SD_STATE);
271 cmd->resp[3] = readl(owl_host->base + OWL_REG_SD_RSPBUF0);
272 cmd->resp[2] = readl(owl_host->base + OWL_REG_SD_RSPBUF1);
273 cmd->resp[1] = readl(owl_host->base + OWL_REG_SD_RSPBUF2);
274 cmd->resp[0] = readl(owl_host->base + OWL_REG_SD_RSPBUF3);
276 resp[0] = readl(owl_host->base + OWL_REG_SD_RSPBUF0);
277 resp[1] = readl(owl_host->base + OWL_REG_SD_RSPBUF1);
298 owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN, OWL_SD_EN_BSEL,
300 writel(data->blocks, owl_host->base + OWL_REG_SD_BLK_NUM);
301 writel(data->blksz, owl_host->base + OWL_REG_SD_BLK_SIZE);
305 writel(total, owl_host->base + OWL_REG_SD_BUF_SIZE);
307 writel(512, owl_host->base + OWL_REG_SD_BUF_SIZE);
395 reg = readl(owl_host->base + OWL_REG_SD_CTL);
402 owl_host->base + OWL_REG_SD_CTL);
406 owl_host->base + OWL_REG_SD_CTL);
410 owl_host->base + OWL_REG_SD_CTL);
415 owl_host->base + OWL_REG_SD_CTL);
441 reg = readl(owl_host->base + OWL_REG_SD_EN);
454 writel(reg, owl_host->base + OWL_REG_SD_EN);
471 owl_mmc_update_reg(owl_host->base + OWL_REG_SD_STATE,
475 mode = (readl(owl_host->base + OWL_REG_SD_CTL) & (0xff << 16));
477 writel(mode, owl_host->base + OWL_REG_SD_CTL);
497 owl_host->base + OWL_REG_SD_EN);
526 owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN,
541 owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN,
545 owl_mmc_update_reg(owl_host->base + OWL_REG_SD_EN,
582 owl_host->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
583 if (IS_ERR(owl_host->base)) {
584 ret = PTR_ERR(owl_host->base);