Lines Matching refs:base
430 void __iomem *base; /* host base address */
431 void __iomem *top_base; /* host top register base address */
671 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST);
672 readl_poll_timeout_atomic(host->base + MSDC_CFG, val, !(val & MSDC_CFG_RST), 0, 0);
674 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR);
675 readl_poll_timeout_atomic(host->base + MSDC_FIFOCS, val,
678 val = readl(host->base + MSDC_INT);
679 writel(val, host->base + MSDC_INT);
757 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
758 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL);
761 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL);
763 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT,
765 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA);
806 sdr_get_field(host->base + MSDC_CFG,
809 sdr_get_field(host->base + MSDC_CFG,
827 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC,
836 sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC,
866 return readl_poll_timeout(host->base + MSDC_CFG, val,
884 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
888 flags = readl(host->base + MSDC_INTEN);
889 sdr_clr_bits(host->base + MSDC_INTEN, flags);
891 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
893 sdr_clr_bits(host->base + MSDC_CFG,
915 sdr_set_bits(host->base + MSDC_CFG,
918 sdr_set_bits(host->base + MSDC_CFG,
937 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
941 sdr_set_field(host->base + MSDC_CFG,
945 sdr_set_field(host->base + MSDC_CFG,
950 readl_poll_timeout(host->base + MSDC_CFG, val, (val & MSDC_CFG_CKSTB), 0, 0);
951 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
957 sdr_set_bits(host->base + MSDC_INTEN, flags);
964 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
972 host->base + tune_reg);
975 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
977 host->base + PAD_CMD_TUNE);
985 host->base + tune_reg);
991 sdr_set_field(host->base + tune_reg,
1069 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO);
1076 writel(data->blocks, host->base + SDC_BLK_NUM);
1092 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask);
1093 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
1104 rsp[0] = readl(host->base + SDC_ACMD_RESP);
1137 reg_inten = readl(host->base + MSDC_INTEN);
1139 reg_int = readl(host->base + MSDC_INT);
1140 reg_ps = readl(host->base + MSDC_PS);
1211 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1215 rsp[0] = readl(host->base + SDC_RESP3);
1216 rsp[1] = readl(host->base + SDC_RESP2);
1217 rsp[2] = readl(host->base + SDC_RESP1);
1218 rsp[3] = readl(host->base + SDC_RESP0);
1220 rsp[0] = readl(host->base + SDC_RESP0);
1262 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val,
1273 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val,
1298 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 ||
1299 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) {
1308 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1311 writel(cmd->arg, host->base + SDC_ARG);
1312 writel(rawcmd, host->base + SDC_CMD);
1414 readl(host->base + MSDC_DMA_CFG));
1415 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP,
1418 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CTRL, val,
1423 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CFG, val,
1428 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask);
1456 u32 val = readl(host->base + SDC_CFG);
1473 writel(val, host->base + SDC_CFG);
1508 u32 status = readl(host->base + MSDC_PS);
1542 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1543 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1547 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1548 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1637 events = readl(host->base + MSDC_INT);
1638 event_mask = readl(host->base + MSDC_INTEN);
1642 writel(events & event_mask, host->base + MSDC_INT);
1665 writel(events, host->base + MSDC_INT);
1701 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
1707 writel(0, host->base + MSDC_INTEN);
1708 val = readl(host->base + MSDC_INT);
1709 writel(val, host->base + MSDC_INT);
1713 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE,
1715 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1716 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1717 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1719 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1720 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1721 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1728 writel(0, host->base + tune_reg);
1730 writel(0, host->base + MSDC_IOCON);
1731 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
1732 writel(0x403c0046, host->base + MSDC_PATCH_BIT);
1733 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
1734 writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
1735 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
1738 sdr_set_field(host->base + MSDC_PATCH_BIT1,
1740 sdr_clr_bits(host->base + SDC_FIFO_CFG,
1742 sdr_clr_bits(host->base + SDC_FIFO_CFG,
1747 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, BIT(7));
1750 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1757 sdr_set_bits(host->base + SDC_ADV_CFG0,
1760 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1762 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1766 sdr_clr_bits(host->base + MSDC_PATCH_BIT2,
1768 sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1773 sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1784 sdr_set_bits(host->base + tune_reg,
1794 sdr_set_bits(host->base + tune_reg,
1799 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1800 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1801 sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
1804 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1807 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1808 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
1812 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
1814 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
1815 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
1826 host->def_tune_para.pad_tune = readl(host->base + tune_reg);
1827 host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
1838 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1839 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1843 writel(0, host->base + MSDC_INTEN);
1845 val = readl(host->base + MSDC_INT);
1846 writel(val, host->base + MSDC_INT);
1991 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
2003 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY,
2021 sdr_set_field(host->base + tune_reg,
2025 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2049 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2074 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2077 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2086 sdr_set_field(host->base + tune_reg,
2094 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY,
2111 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0));
2112 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2);
2116 sdr_set_field(host->base + MSDC_PAD_TUNE,
2121 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2123 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2125 sdr_set_field(host->base + PAD_CMD_TUNE,
2143 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3,
2159 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2161 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2162 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2175 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2176 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2188 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2189 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2192 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2193 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2214 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2217 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2218 sdr_clr_bits(host->base + MSDC_IOCON,
2233 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2234 sdr_set_bits(host->base + MSDC_IOCON,
2248 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2249 sdr_clr_bits(host->base + MSDC_IOCON,
2253 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2254 sdr_set_bits(host->base + MSDC_IOCON,
2275 sdr_clr_bits(host->base + MSDC_IOCON,
2297 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
2298 host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
2299 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2318 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
2320 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
2322 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2);
2342 sdr_set_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY_SEL);
2344 sdr_set_field(host->base + PAD_DS_TUNE,
2354 sdr_set_field(host->base + PAD_DS_TUNE,
2373 sdr_set_field(host->base + PAD_DS_TUNE,
2379 val = readl(host->base + PAD_DS_TUNE);
2394 sdr_set_bits(host->base + EMMC_IOCON, 1);
2396 sdr_clr_bits(host->base + EMMC_IOCON, 1);
2420 val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS;
2434 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 1);
2435 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 1);
2436 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 1);
2438 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL);
2439 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL);
2440 sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT);
2442 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 0);
2443 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 0);
2444 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 0);
2446 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL);
2447 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL);
2448 sdr_set_field(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT, 0xb4);
2497 writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN);
2499 sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2515 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ);
2517 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2519 val = readl(host->base + MSDC_INT);
2520 writel(val, host->base + MSDC_INT);
2523 sdr_set_field(host->base + MSDC_DMA_CTRL,
2525 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CTRL, val,
2528 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val,
2686 host->base = devm_platform_ioremap_resource(pdev, 0);
2687 if (IS_ERR(host->base)) {
2688 ret = PTR_ERR(host->base);
2839 host->cq_host->mmio = host->base + 0x800;
2918 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
2919 host->save_para.iocon = readl(host->base + MSDC_IOCON);
2920 host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
2921 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
2922 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
2923 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2);
2924 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
2925 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2926 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
2927 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3);
2928 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
2937 host->save_para.pad_tune = readl(host->base + tune_reg);
2946 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
2947 writel(host->save_para.iocon, host->base + MSDC_IOCON);
2948 writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
2949 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
2950 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
2951 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2);
2952 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
2953 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
2954 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
2955 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3);
2956 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
2965 writel(host->save_para.pad_tune, host->base + tune_reg);
3021 val = readl(host->base + MSDC_INT);
3022 writel(val, host->base + MSDC_INT);