Lines Matching defs:host
30 #include <linux/mmc/host.h>
430 void __iomem *base; /* host base address */
431 void __iomem *top_base; /* host top register base address */
444 int irq; /* host interrupt */
667 static void msdc_reset_hw(struct msdc_host *host)
671 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST);
672 readl_poll_timeout_atomic(host->base + MSDC_CFG, val, !(val & MSDC_CFG_RST), 0, 0);
674 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR);
675 readl_poll_timeout_atomic(host->base + MSDC_FIFOCS, val,
678 val = readl(host->base + MSDC_INT);
679 writel(val, host->base + MSDC_INT);
682 static void msdc_cmd_next(struct msdc_host *host,
684 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb);
702 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
733 if (host->dev_comp->support_64g) {
739 if (host->dev_comp->support_64g) {
757 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
758 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL);
761 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL);
762 if (host->dev_comp->support_64g)
763 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT,
765 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA);
768 static void msdc_prepare_data(struct msdc_host *host, struct mmc_data *data)
772 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len,
777 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_data *data)
783 dma_unmap_sg(host->dev, data->sg, data->sg_len,
789 static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks)
791 struct mmc_host *mmc = mmc_from_priv(host);
805 if (host->dev_comp->clk_div_bits == 8)
806 sdr_get_field(host->base + MSDC_CFG,
809 sdr_get_field(host->base + MSDC_CFG,
819 static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks)
823 host->timeout_ns = ns;
824 host->timeout_clks = clks;
826 timeout = msdc_timeout_cal(host, ns, clks);
827 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC,
831 static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks)
835 timeout = msdc_timeout_cal(host, ns, clks);
836 sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC,
840 static void msdc_gate_clock(struct msdc_host *host)
842 clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks);
843 clk_disable_unprepare(host->crypto_clk);
844 clk_disable_unprepare(host->src_clk_cg);
845 clk_disable_unprepare(host->src_clk);
846 clk_disable_unprepare(host->bus_clk);
847 clk_disable_unprepare(host->h_clk);
850 static int msdc_ungate_clock(struct msdc_host *host)
855 clk_prepare_enable(host->h_clk);
856 clk_prepare_enable(host->bus_clk);
857 clk_prepare_enable(host->src_clk);
858 clk_prepare_enable(host->src_clk_cg);
859 clk_prepare_enable(host->crypto_clk);
860 ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks);
862 dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n");
866 return readl_poll_timeout(host->base + MSDC_CFG, val,
870 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
872 struct mmc_host *mmc = mmc_from_priv(host);
877 u32 tune_reg = host->dev_comp->pad_tune_reg;
881 dev_dbg(host->dev, "set mclk to 0\n");
882 host->mclk = 0;
884 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
888 flags = readl(host->base + MSDC_INTEN);
889 sdr_clr_bits(host->base + MSDC_INTEN, flags);
890 if (host->dev_comp->clk_div_bits == 8)
891 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
893 sdr_clr_bits(host->base + MSDC_CFG,
903 if (hz >= (host->src_clk_freq >> 2)) {
905 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
907 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
908 sclk = (host->src_clk_freq >> 2) / div;
913 hz >= (host->src_clk_freq >> 1)) {
914 if (host->dev_comp->clk_div_bits == 8)
915 sdr_set_bits(host->base + MSDC_CFG,
918 sdr_set_bits(host->base + MSDC_CFG,
920 sclk = host->src_clk_freq >> 1;
923 } else if (hz >= host->src_clk_freq) {
926 sclk = host->src_clk_freq;
929 if (hz >= (host->src_clk_freq >> 1)) {
931 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
933 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
934 sclk = (host->src_clk_freq >> 2) / div;
937 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
939 clk_disable_unprepare(host->src_clk_cg);
940 if (host->dev_comp->clk_div_bits == 8)
941 sdr_set_field(host->base + MSDC_CFG,
945 sdr_set_field(host->base + MSDC_CFG,
949 clk_prepare_enable(host->src_clk_cg);
950 readl_poll_timeout(host->base + MSDC_CFG, val, (val & MSDC_CFG_CKSTB), 0, 0);
951 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
953 host->mclk = hz;
954 host->timing = timing;
956 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
957 sdr_set_bits(host->base + MSDC_INTEN, flags);
964 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
965 if (host->top_base) {
966 writel(host->def_tune_para.emmc_top_control,
967 host->top_base + EMMC_TOP_CONTROL);
968 writel(host->def_tune_para.emmc_top_cmd,
969 host->top_base + EMMC_TOP_CMD);
971 writel(host->def_tune_para.pad_tune,
972 host->base + tune_reg);
975 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
976 writel(host->saved_tune_para.pad_cmd_tune,
977 host->base + PAD_CMD_TUNE);
978 if (host->top_base) {
979 writel(host->saved_tune_para.emmc_top_control,
980 host->top_base + EMMC_TOP_CONTROL);
981 writel(host->saved_tune_para.emmc_top_cmd,
982 host->top_base + EMMC_TOP_CMD);
984 writel(host->saved_tune_para.pad_tune,
985 host->base + tune_reg);
990 host->dev_comp->hs400_tune)
991 sdr_set_field(host->base + tune_reg,
993 host->hs400_cmd_int_delay);
994 dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock,
998 static inline u32 msdc_cmd_find_resp(struct msdc_host *host,
1026 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
1029 struct mmc_host *mmc = mmc_from_priv(host);
1035 u32 resp = msdc_cmd_find_resp(host, cmd);
1038 host->cmd_rsp = resp;
1069 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO);
1071 if (host->timeout_ns != data->timeout_ns ||
1072 host->timeout_clks != data->timeout_clks)
1073 msdc_set_timeout(host, data->timeout_ns,
1076 writel(data->blocks, host->base + SDC_BLK_NUM);
1081 static void msdc_start_data(struct msdc_host *host, struct mmc_command *cmd,
1086 WARN_ON(host->data);
1087 host->data = data;
1090 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
1091 msdc_dma_setup(host, &host->dma, data);
1092 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask);
1093 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
1094 dev_dbg(host->dev, "DMA start\n");
1095 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n",
1099 static int msdc_auto_cmd_done(struct msdc_host *host, int events,
1104 rsp[0] = readl(host->base + SDC_ACMD_RESP);
1109 msdc_reset_hw(host);
1112 host->error |= REQ_STOP_EIO;
1115 host->error |= REQ_STOP_TMO;
1117 dev_err(host->dev,
1131 static void msdc_recheck_sdio_irq(struct msdc_host *host)
1133 struct mmc_host *mmc = mmc_from_priv(host);
1137 reg_inten = readl(host->base + MSDC_INTEN);
1139 reg_int = readl(host->base + MSDC_INT);
1140 reg_ps = readl(host->base + MSDC_PS);
1143 __msdc_enable_sdio_irq(host, 0);
1150 static void msdc_track_cmd_data(struct msdc_host *host, struct mmc_command *cmd)
1152 if (host->error)
1153 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n",
1154 __func__, cmd->opcode, cmd->arg, host->error);
1157 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq)
1165 cancel_delayed_work(&host->req_timeout);
1167 spin_lock_irqsave(&host->lock, flags);
1168 host->mrq = NULL;
1169 spin_unlock_irqrestore(&host->lock, flags);
1171 msdc_track_cmd_data(host, mrq->cmd);
1173 msdc_unprepare_data(host, mrq->data);
1174 if (host->error)
1175 msdc_reset_hw(host);
1176 mmc_request_done(mmc_from_priv(host), mrq);
1177 if (host->dev_comp->recheck_sdio_irq)
1178 msdc_recheck_sdio_irq(host);
1182 static bool msdc_cmd_done(struct msdc_host *host, int events,
1193 msdc_auto_cmd_done(host, events, mrq->sbc);
1202 spin_lock_irqsave(&host->lock, flags);
1203 done = !host->cmd;
1204 host->cmd = NULL;
1205 spin_unlock_irqrestore(&host->lock, flags);
1211 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1215 rsp[0] = readl(host->base + SDC_RESP3);
1216 rsp[1] = readl(host->base + SDC_RESP2);
1217 rsp[2] = readl(host->base + SDC_RESP1);
1218 rsp[3] = readl(host->base + SDC_RESP0);
1220 rsp[0] = readl(host->base + SDC_RESP0);
1226 (!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning))
1232 msdc_reset_hw(host);
1235 host->error |= REQ_CMD_EIO;
1238 host->error |= REQ_CMD_TMO;
1242 dev_dbg(host->dev,
1247 msdc_cmd_next(host, mrq, cmd);
1252 * is correct before issue a request. but host design do below
1255 static inline bool msdc_cmd_is_ready(struct msdc_host *host,
1262 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val,
1265 dev_err(host->dev, "CMD bus busy detected\n");
1266 host->error |= REQ_CMD_BUSY;
1267 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1273 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val,
1276 dev_err(host->dev, "Controller busy detected\n");
1277 host->error |= REQ_CMD_BUSY;
1278 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1285 static void msdc_start_command(struct msdc_host *host,
1291 WARN_ON(host->cmd);
1292 host->cmd = cmd;
1294 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
1295 if (!msdc_cmd_is_ready(host, mrq, cmd))
1298 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 ||
1299 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) {
1300 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n");
1301 msdc_reset_hw(host);
1305 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd);
1307 spin_lock_irqsave(&host->lock, flags);
1308 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1309 spin_unlock_irqrestore(&host->lock, flags);
1311 writel(cmd->arg, host->base + SDC_ARG);
1312 writel(rawcmd, host->base + SDC_CMD);
1315 static void msdc_cmd_next(struct msdc_host *host,
1320 (mmc_op_tuning(cmd->opcode) || host->hs400_tuning))) ||
1322 msdc_request_done(host, mrq);
1324 msdc_start_command(host, mrq, mrq->cmd);
1326 msdc_request_done(host, mrq);
1328 msdc_start_data(host, cmd, cmd->data);
1333 struct msdc_host *host = mmc_priv(mmc);
1335 host->error = 0;
1336 WARN_ON(host->mrq);
1337 host->mrq = mrq;
1340 msdc_prepare_data(host, mrq->data);
1348 msdc_start_command(host, mrq, mrq->sbc);
1350 msdc_start_command(host, mrq, mrq->cmd);
1355 struct msdc_host *host = mmc_priv(mmc);
1361 msdc_prepare_data(host, data);
1368 struct msdc_host *host = mmc_priv(mmc);
1376 msdc_unprepare_data(host, data);
1380 static void msdc_data_xfer_next(struct msdc_host *host, struct mmc_request *mrq)
1384 msdc_start_command(host, mrq, mrq->stop);
1386 msdc_request_done(host, mrq);
1389 static void msdc_data_xfer_done(struct msdc_host *host, u32 events,
1402 spin_lock_irqsave(&host->lock, flags);
1403 done = !host->data;
1405 host->data = NULL;
1406 spin_unlock_irqrestore(&host->lock, flags);
1413 dev_dbg(host->dev, "DMA status: 0x%8X\n",
1414 readl(host->base + MSDC_DMA_CFG));
1415 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP,
1418 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CTRL, val,
1421 dev_dbg(host->dev, "DMA stop timed out\n");
1423 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CFG, val,
1426 dev_dbg(host->dev, "DMA inactive timed out\n");
1428 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask);
1429 dev_dbg(host->dev, "DMA stop\n");
1434 dev_dbg(host->dev, "interrupt events: %x\n", events);
1435 msdc_reset_hw(host);
1436 host->error |= REQ_DAT_ERR;
1444 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d",
1446 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n",
1450 msdc_data_xfer_next(host, mrq);
1454 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
1456 u32 val = readl(host->base + SDC_CFG);
1473 writel(val, host->base + SDC_CFG);
1474 dev_dbg(host->dev, "Bus Width = %d", width);
1479 struct msdc_host *host = mmc_priv(mmc);
1485 dev_err(host->dev, "Unsupported signal voltage!\n");
1491 dev_dbg(host->dev, "Regulator set error %d (%d)\n",
1498 pinctrl_select_state(host->pinctrl, host->pins_uhs);
1500 pinctrl_select_state(host->pinctrl, host->pins_default);
1507 struct msdc_host *host = mmc_priv(mmc);
1508 u32 status = readl(host->base + MSDC_PS);
1516 struct msdc_host *host = container_of(work, struct msdc_host,
1520 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__);
1521 if (host->mrq) {
1522 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__,
1523 host->mrq, host->mrq->cmd->opcode);
1524 if (host->cmd) {
1525 dev_err(host->dev, "%s: aborting cmd=%d\n",
1526 __func__, host->cmd->opcode);
1527 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq,
1528 host->cmd);
1529 } else if (host->data) {
1530 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n",
1531 __func__, host->mrq->cmd->opcode,
1532 host->data->blocks);
1533 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq,
1534 host->data);
1539 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb)
1542 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1543 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1544 if (host->dev_comp->recheck_sdio_irq)
1545 msdc_recheck_sdio_irq(host);
1547 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1548 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1554 struct msdc_host *host = mmc_priv(mmc);
1558 spin_lock_irqsave(&host->lock, flags);
1559 __msdc_enable_sdio_irq(host, enb);
1560 spin_unlock_irqrestore(&host->lock, flags);
1562 if (mmc_card_enable_async_irq(mmc->card) && host->pins_eint) {
1570 pinctrl_select_state(host->pinctrl, host->pins_eint);
1571 ret = dev_pm_set_dedicated_wake_irq_reverse(host->dev, host->eint_irq);
1574 dev_err(host->dev, "Failed to register SDIO wakeup irq!\n");
1575 host->pins_eint = NULL;
1576 pm_runtime_get_noresume(host->dev);
1578 dev_dbg(host->dev, "SDIO eint irq: %d!\n", host->eint_irq);
1581 pinctrl_select_state(host->pinctrl, host->pins_uhs);
1583 dev_pm_clear_wake_irq(host->dev);
1587 /* Ensure host->pins_eint is NULL */
1588 host->pins_eint = NULL;
1589 pm_runtime_get_noresume(host->dev);
1591 pm_runtime_put_noidle(host->dev);
1596 static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts)
1598 struct mmc_host *mmc = mmc_from_priv(host);
1603 dev_err(host->dev, "%s: CMD CRC ERR", __func__);
1606 dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__);
1611 dev_err(host->dev, "%s: DATA CRC ERR", __func__);
1614 dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__);
1618 dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x",
1627 struct msdc_host *host = (struct msdc_host *) dev_id;
1628 struct mmc_host *mmc = mmc_from_priv(host);
1636 spin_lock(&host->lock);
1637 events = readl(host->base + MSDC_INT);
1638 event_mask = readl(host->base + MSDC_INTEN);
1640 __msdc_enable_sdio_irq(host, 0);
1642 writel(events & event_mask, host->base + MSDC_INT);
1644 mrq = host->mrq;
1645 cmd = host->cmd;
1646 data = host->data;
1647 spin_unlock(&host->lock);
1653 if (host->internal_cd)
1663 msdc_cmdq_irq(host, events);
1665 writel(events, host->base + MSDC_INT);
1670 dev_err(host->dev,
1677 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events);
1680 msdc_cmd_done(host, events, mrq, cmd);
1682 msdc_data_xfer_done(host, events, mrq, data);
1688 static void msdc_init_hw(struct msdc_host *host)
1691 u32 tune_reg = host->dev_comp->pad_tune_reg;
1692 struct mmc_host *mmc = mmc_from_priv(host);
1694 if (host->reset) {
1695 reset_control_assert(host->reset);
1697 reset_control_deassert(host->reset);
1701 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
1704 msdc_reset_hw(host);
1707 writel(0, host->base + MSDC_INTEN);
1708 val = readl(host->base + MSDC_INT);
1709 writel(val, host->base + MSDC_INT);
1712 if (host->internal_cd) {
1713 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE,
1715 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1716 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1717 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1719 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1720 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1721 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1724 if (host->top_base) {
1725 writel(0, host->top_base + EMMC_TOP_CONTROL);
1726 writel(0, host->top_base + EMMC_TOP_CMD);
1728 writel(0, host->base + tune_reg);
1730 writel(0, host->base + MSDC_IOCON);
1731 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
1732 writel(0x403c0046, host->base + MSDC_PATCH_BIT);
1733 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
1734 writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
1735 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
1737 if (host->dev_comp->stop_clk_fix) {
1738 sdr_set_field(host->base + MSDC_PATCH_BIT1,
1740 sdr_clr_bits(host->base + SDC_FIFO_CFG,
1742 sdr_clr_bits(host->base + SDC_FIFO_CFG,
1746 if (host->dev_comp->busy_check)
1747 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, BIT(7));
1749 if (host->dev_comp->async_fifo) {
1750 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1752 if (host->dev_comp->enhance_rx) {
1753 if (host->top_base)
1754 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1757 sdr_set_bits(host->base + SDC_ADV_CFG0,
1760 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1762 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1766 sdr_clr_bits(host->base + MSDC_PATCH_BIT2,
1768 sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1772 if (host->dev_comp->support_64g)
1773 sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1775 if (host->dev_comp->data_tune) {
1776 if (host->top_base) {
1777 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1779 sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL,
1781 sdr_set_bits(host->top_base + EMMC_TOP_CMD,
1784 sdr_set_bits(host->base + tune_reg,
1790 if (host->top_base)
1791 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1794 sdr_set_bits(host->base + tune_reg,
1799 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1800 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1801 sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
1804 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1807 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1808 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
1812 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
1814 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
1815 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
1816 if (host->top_base) {
1817 host->def_tune_para.emmc_top_control =
1818 readl(host->top_base + EMMC_TOP_CONTROL);
1819 host->def_tune_para.emmc_top_cmd =
1820 readl(host->top_base + EMMC_TOP_CMD);
1821 host->saved_tune_para.emmc_top_control =
1822 readl(host->top_base + EMMC_TOP_CONTROL);
1823 host->saved_tune_para.emmc_top_cmd =
1824 readl(host->top_base + EMMC_TOP_CMD);
1826 host->def_tune_para.pad_tune = readl(host->base + tune_reg);
1827 host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
1829 dev_dbg(host->dev, "init hardware done!");
1832 static void msdc_deinit_hw(struct msdc_host *host)
1836 if (host->internal_cd) {
1838 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1839 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1843 writel(0, host->base + MSDC_INTEN);
1845 val = readl(host->base + MSDC_INT);
1846 writel(val, host->base + MSDC_INT);
1850 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
1865 if (host->dev_comp->support_64g)
1870 if (host->dev_comp->support_64g)
1877 if (host->dev_comp->support_64g)
1884 struct msdc_host *host = mmc_priv(mmc);
1887 msdc_set_buswidth(host, ios->bus_width);
1893 msdc_init_hw(host);
1897 dev_err(host->dev, "Failed to set vmmc power!\n");
1903 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1906 dev_err(host->dev, "Failed to set vqmmc power!\n");
1908 host->vqmmc_enabled = true;
1915 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1917 host->vqmmc_enabled = false;
1924 if (host->mclk != ios->clock || host->timing != ios->timing)
1925 msdc_set_mclk(host, ios->timing, ios->clock);
1945 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
1953 dev_err(host->dev, "phase error: [map:%x]\n", delay);
1974 dev_dbg(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n",
1983 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)
1985 u32 tune_reg = host->dev_comp->pad_tune_reg;
1987 if (host->top_base)
1988 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY,
1991 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
1995 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
1997 u32 tune_reg = host->dev_comp->pad_tune_reg;
1999 if (host->top_base)
2000 sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
2003 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY,
2009 struct msdc_host *host = mmc_priv(mmc);
2015 u32 tune_reg = host->dev_comp->pad_tune_reg;
2021 sdr_set_field(host->base + tune_reg,
2023 host->hs200_cmd_int_delay);
2025 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2027 msdc_set_cmd_delay(host, i);
2043 final_rise_delay = get_best_delay(host, rise_delay);
2049 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2051 msdc_set_cmd_delay(host, i);
2067 final_fall_delay = get_best_delay(host, fall_delay);
2074 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2077 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2080 msdc_set_cmd_delay(host, final_delay);
2082 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
2086 sdr_set_field(host->base + tune_reg,
2092 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay);
2093 internal_delay_phase = get_best_delay(host, internal_delay);
2094 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY,
2097 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
2103 struct msdc_host *host = mmc_priv(mmc);
2111 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0));
2112 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2);
2116 sdr_set_field(host->base + MSDC_PAD_TUNE,
2118 host->hs200_cmd_int_delay);
2120 if (host->hs400_cmd_resp_sel_rising)
2121 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2123 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2125 sdr_set_field(host->base + PAD_CMD_TUNE,
2142 final_cmd_delay = get_best_delay(host, cmd_delay);
2143 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3,
2147 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
2153 struct msdc_host *host = mmc_priv(mmc);
2159 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2160 host->latch_ck);
2161 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2162 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2164 msdc_set_data_delay(host, i);
2169 final_rise_delay = get_best_delay(host, rise_delay);
2175 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2176 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2178 msdc_set_data_delay(host, i);
2183 final_fall_delay = get_best_delay(host, fall_delay);
2188 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2189 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2192 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2193 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2196 msdc_set_data_delay(host, final_delay);
2198 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay);
2208 struct msdc_host *host = mmc_priv(mmc);
2214 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2215 host->latch_ck);
2217 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2218 sdr_clr_bits(host->base + MSDC_IOCON,
2221 msdc_set_cmd_delay(host, i);
2222 msdc_set_data_delay(host, i);
2227 final_rise_delay = get_best_delay(host, rise_delay);
2233 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2234 sdr_set_bits(host->base + MSDC_IOCON,
2237 msdc_set_cmd_delay(host, i);
2238 msdc_set_data_delay(host, i);
2243 final_fall_delay = get_best_delay(host, fall_delay);
2248 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2249 sdr_clr_bits(host->base + MSDC_IOCON,
2253 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2254 sdr_set_bits(host->base + MSDC_IOCON,
2259 msdc_set_cmd_delay(host, final_delay);
2260 msdc_set_data_delay(host, final_delay);
2262 dev_dbg(host->dev, "Final pad delay: %x\n", final_delay);
2268 struct msdc_host *host = mmc_priv(mmc);
2270 u32 tune_reg = host->dev_comp->pad_tune_reg;
2272 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) {
2274 if (host->hs400_mode) {
2275 sdr_clr_bits(host->base + MSDC_IOCON,
2277 msdc_set_data_delay(host, 0);
2281 if (host->hs400_mode &&
2282 host->dev_comp->hs400_tune)
2287 dev_err(host->dev, "Tune response fail!\n");
2290 if (host->hs400_mode == false) {
2293 dev_err(host->dev, "Tune data fail!\n");
2297 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
2298 host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
2299 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2300 if (host->top_base) {
2301 host->saved_tune_para.emmc_top_control = readl(host->top_base +
2303 host->saved_tune_para.emmc_top_cmd = readl(host->top_base +
2311 struct msdc_host *host = mmc_priv(mmc);
2312 host->hs400_mode = true;
2314 if (host->top_base)
2315 writel(host->hs400_ds_delay,
2316 host->top_base + EMMC50_PAD_DS_TUNE);
2318 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
2320 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
2322 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2);
2329 struct msdc_host *host = mmc_priv(mmc);
2335 if (host->top_base) {
2336 sdr_set_bits(host->top_base + EMMC50_PAD_DS_TUNE,
2338 if (host->hs400_ds_dly3)
2339 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2340 PAD_DS_DLY3, host->hs400_ds_dly3);
2342 sdr_set_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY_SEL);
2343 if (host->hs400_ds_dly3)
2344 sdr_set_field(host->base + PAD_DS_TUNE,
2345 PAD_DS_TUNE_DLY3, host->hs400_ds_dly3);
2348 host->hs400_tuning = true;
2350 if (host->top_base)
2351 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2354 sdr_set_field(host->base + PAD_DS_TUNE,
2362 host->hs400_tuning = false;
2364 dly1_delay = get_best_delay(host, result_dly1);
2366 dev_err(host->dev, "Failed to get DLY1 delay!\n");
2369 if (host->top_base)
2370 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2373 sdr_set_field(host->base + PAD_DS_TUNE,
2376 if (host->top_base)
2377 val = readl(host->top_base + EMMC50_PAD_DS_TUNE);
2379 val = readl(host->base + PAD_DS_TUNE);
2381 dev_info(host->dev, "Final PAD_DS_TUNE: 0x%x\n", val);
2386 dev_err(host->dev, "Failed to tuning DS pin delay!\n");
2392 struct msdc_host *host = mmc_priv(mmc);
2394 sdr_set_bits(host->base + EMMC_IOCON, 1);
2396 sdr_clr_bits(host->base + EMMC_IOCON, 1);
2402 struct msdc_host *host = mmc_priv(mmc);
2404 spin_lock_irqsave(&host->lock, flags);
2405 __msdc_enable_sdio_irq(host, 1);
2406 spin_unlock_irqrestore(&host->lock, flags);
2411 struct msdc_host *host = mmc_priv(mmc);
2417 if (!host->internal_cd)
2420 val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS;
2430 struct msdc_host *host = mmc_priv(mmc);
2434 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 1);
2435 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 1);
2436 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 1);
2438 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL);
2439 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL);
2440 sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT);
2442 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 0);
2443 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 0);
2444 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 0);
2446 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL);
2447 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL);
2448 sdr_set_field(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT, 0xb4);
2452 static void msdc_cqe_cit_cal(struct msdc_host *host, u64 timer_ns)
2454 struct mmc_host *mmc = mmc_from_priv(host);
2464 hclk_freq = (u64)clk_get_rate(host->h_clk);
2482 host->cq_ssc1_time = 0x40;
2488 host->cq_ssc1_time = value;
2493 struct msdc_host *host = mmc_priv(mmc);
2497 writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN);
2499 sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2501 msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0);
2503 msdc_set_timeout(host, 1000000000ULL, 0);
2506 cqhci_writel(cq_host, host->cq_ssc1_time, CQHCI_SSC1);
2511 struct msdc_host *host = mmc_priv(mmc);
2515 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ);
2517 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2519 val = readl(host->base + MSDC_INT);
2520 writel(val, host->base + MSDC_INT);
2523 sdr_set_field(host->base + MSDC_DMA_CTRL,
2525 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CTRL, val,
2528 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val,
2531 msdc_reset_hw(host);
2581 struct msdc_host *host)
2584 &host->latch_ck);
2587 &host->hs400_ds_delay);
2590 &host->hs400_ds_dly3);
2593 &host->hs200_cmd_int_delay);
2596 &host->hs400_cmd_int_delay);
2600 host->hs400_cmd_resp_sel_rising = true;
2602 host->hs400_cmd_resp_sel_rising = false;
2606 host->cqhci = true;
2608 host->cqhci = false;
2612 struct msdc_host *host)
2616 host->src_clk = devm_clk_get(&pdev->dev, "source");
2617 if (IS_ERR(host->src_clk))
2618 return PTR_ERR(host->src_clk);
2620 host->h_clk = devm_clk_get(&pdev->dev, "hclk");
2621 if (IS_ERR(host->h_clk))
2622 return PTR_ERR(host->h_clk);
2624 host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk");
2625 if (IS_ERR(host->bus_clk))
2626 host->bus_clk = NULL;
2629 host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg");
2630 if (IS_ERR(host->src_clk_cg))
2631 return PTR_ERR(host->src_clk_cg);
2640 if (!host->src_clk_cg) {
2641 host->src_clk_cg = clk_get_parent(host->src_clk);
2642 if (IS_ERR(host->src_clk_cg))
2643 return PTR_ERR(host->src_clk_cg);
2647 host->sys_clk_cg = devm_clk_get_optional_enabled(&pdev->dev, "sys_cg");
2648 if (IS_ERR(host->sys_clk_cg))
2649 host->sys_clk_cg = NULL;
2651 host->bulk_clks[0].id = "pclk_cg";
2652 host->bulk_clks[1].id = "axi_cg";
2653 host->bulk_clks[2].id = "ahb_cg";
2655 host->bulk_clks);
2667 struct msdc_host *host;
2676 /* Allocate MMC host for this device */
2681 host = mmc_priv(mmc);
2686 host->base = devm_platform_ioremap_resource(pdev, 0);
2687 if (IS_ERR(host->base)) {
2688 ret = PTR_ERR(host->base);
2694 host->top_base = devm_ioremap_resource(&pdev->dev, res);
2695 if (IS_ERR(host->top_base))
2696 host->top_base = NULL;
2703 ret = msdc_of_clock_parse(pdev, host);
2707 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
2709 if (IS_ERR(host->reset)) {
2710 ret = PTR_ERR(host->reset);
2716 host->crypto_clk = devm_clk_get_optional(&pdev->dev, "crypto");
2717 if (IS_ERR(host->crypto_clk))
2718 host->crypto_clk = NULL;
2723 host->irq = platform_get_irq(pdev, 0);
2724 if (host->irq < 0) {
2725 ret = host->irq;
2729 host->pinctrl = devm_pinctrl_get(&pdev->dev);
2730 if (IS_ERR(host->pinctrl)) {
2731 ret = PTR_ERR(host->pinctrl);
2736 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default");
2737 if (IS_ERR(host->pins_default)) {
2738 ret = PTR_ERR(host->pins_default);
2743 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs");
2744 if (IS_ERR(host->pins_uhs)) {
2745 ret = PTR_ERR(host->pins_uhs);
2752 host->eint_irq = platform_get_irq_byname_optional(pdev, "sdio_wakeup");
2753 if (host->eint_irq > 0) {
2754 host->pins_eint = pinctrl_lookup_state(host->pinctrl, "state_eint");
2755 if (IS_ERR(host->pins_eint)) {
2757 host->pins_eint = NULL;
2764 msdc_of_property_parse(pdev, host);
2766 host->dev = &pdev->dev;
2767 host->dev_comp = of_device_get_match_data(&pdev->dev);
2768 host->src_clk_freq = clk_get_rate(host->src_clk);
2769 /* Set host parameters to mmc */
2771 if (host->dev_comp->clk_div_bits == 8)
2772 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
2774 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095);
2778 host->dev_comp->use_internal_cd) {
2783 host->internal_cd = true;
2790 if (host->cqhci)
2794 if (host->dev_comp->support_64g)
2801 if (host->dev_comp->support_64g)
2802 host->dma_mask = DMA_BIT_MASK(36);
2804 host->dma_mask = DMA_BIT_MASK(32);
2805 mmc_dev(mmc)->dma_mask = &host->dma_mask;
2807 host->timeout_clks = 3 * 1048576;
2808 host->dma.gpd = dma_alloc_coherent(&pdev->dev,
2810 &host->dma.gpd_addr, GFP_KERNEL);
2811 host->dma.bd = dma_alloc_coherent(&pdev->dev,
2813 &host->dma.bd_addr, GFP_KERNEL);
2814 if (!host->dma.gpd || !host->dma.bd) {
2818 msdc_init_gpd_bd(host, &host->dma);
2819 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout);
2820 spin_lock_init(&host->lock);
2823 ret = msdc_ungate_clock(host);
2828 msdc_init_hw(host);
2831 host->cq_host = devm_kzalloc(mmc->parent,
2832 sizeof(*host->cq_host),
2834 if (!host->cq_host) {
2838 host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
2839 host->cq_host->mmio = host->base + 0x800;
2840 host->cq_host->ops = &msdc_cmdq_ops;
2841 ret = cqhci_init(host->cq_host, mmc, true);
2849 msdc_cqe_cit_cal(host, 2350);
2852 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq,
2853 IRQF_TRIGGER_NONE, pdev->name, host);
2857 pm_runtime_set_active(host->dev);
2858 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY);
2859 pm_runtime_use_autosuspend(host->dev);
2860 pm_runtime_enable(host->dev);
2868 pm_runtime_disable(host->dev);
2871 msdc_deinit_hw(host);
2872 msdc_gate_clock(host);
2874 if (host->dma.gpd)
2877 host->dma.gpd, host->dma.gpd_addr);
2878 if (host->dma.bd)
2881 host->dma.bd, host->dma.bd_addr);
2891 struct msdc_host *host;
2894 host = mmc_priv(mmc);
2896 pm_runtime_get_sync(host->dev);
2900 msdc_deinit_hw(host);
2901 msdc_gate_clock(host);
2903 pm_runtime_disable(host->dev);
2904 pm_runtime_put_noidle(host->dev);
2907 host->dma.gpd, host->dma.gpd_addr);
2909 host->dma.bd, host->dma.bd_addr);
2914 static void msdc_save_reg(struct msdc_host *host)
2916 u32 tune_reg = host->dev_comp->pad_tune_reg;
2918 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
2919 host->save_para.iocon = readl(host->base + MSDC_IOCON);
2920 host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
2921 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
2922 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
2923 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2);
2924 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
2925 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2926 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
2927 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3);
2928 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
2929 if (host->top_base) {
2930 host->save_para.emmc_top_control =
2931 readl(host->top_base + EMMC_TOP_CONTROL);
2932 host->save_para.emmc_top_cmd =
2933 readl(host->top_base + EMMC_TOP_CMD);
2934 host->save_para.emmc50_pad_ds_tune =
2935 readl(host->top_base + EMMC50_PAD_DS_TUNE);
2937 host->save_para.pad_tune = readl(host->base + tune_reg);
2941 static void msdc_restore_reg(struct msdc_host *host)
2943 struct mmc_host *mmc = mmc_from_priv(host);
2944 u32 tune_reg = host->dev_comp->pad_tune_reg;
2946 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
2947 writel(host->save_para.iocon, host->base + MSDC_IOCON);
2948 writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
2949 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
2950 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
2951 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2);
2952 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
2953 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
2954 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
2955 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3);
2956 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
2957 if (host->top_base) {
2958 writel(host->save_para.emmc_top_control,
2959 host->top_base + EMMC_TOP_CONTROL);
2960 writel(host->save_para.emmc_top_cmd,
2961 host->top_base + EMMC_TOP_CMD);
2962 writel(host->save_para.emmc50_pad_ds_tune,
2963 host->top_base + EMMC50_PAD_DS_TUNE);
2965 writel(host->save_para.pad_tune, host->base + tune_reg);
2969 __msdc_enable_sdio_irq(host, 1);
2975 struct msdc_host *host = mmc_priv(mmc);
2977 msdc_save_reg(host);
2980 if (host->pins_eint) {
2981 disable_irq(host->irq);
2982 pinctrl_select_state(host->pinctrl, host->pins_eint);
2985 __msdc_enable_sdio_irq(host, 0);
2987 msdc_gate_clock(host);
2994 struct msdc_host *host = mmc_priv(mmc);
2997 ret = msdc_ungate_clock(host);
3001 msdc_restore_reg(host);
3003 if (sdio_irq_claimed(mmc) && host->pins_eint) {
3004 pinctrl_select_state(host->pinctrl, host->pins_uhs);
3005 enable_irq(host->irq);
3013 struct msdc_host *host = mmc_priv(mmc);
3021 val = readl(host->base + MSDC_INT);
3022 writel(val, host->base + MSDC_INT);
3029 if (sdio_irq_claimed(mmc) && host->pins_eint)
3038 struct msdc_host *host = mmc_priv(mmc);
3040 if (sdio_irq_claimed(mmc) && host->pins_eint)