Lines Matching defs:data
427 struct mmc_data *data;
436 u32 timeout_ns; /* data timeout ns */
437 u32 timeout_clks; /* data timeout clks */
619 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
620 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
621 { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat},
622 { .compatible = "mediatek,mt6795-mmc", .data = &mt6795_compat},
623 { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat},
624 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
625 { .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat},
626 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
627 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
628 { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat},
629 { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat},
703 struct mmc_data *data)
712 sg = data->sg;
725 for_each_sg(data->sg, sg, data->sg_count, j) {
747 if (j == data->sg_count - 1) /* the last bd */
768 static void msdc_prepare_data(struct msdc_host *host, struct mmc_data *data)
770 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) {
771 data->host_cookie |= MSDC_PREPARE_FLAG;
772 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len,
773 mmc_get_dma_dir(data));
777 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_data *data)
779 if (data->host_cookie & MSDC_ASYNC_FLAG)
782 if (data->host_cookie & MSDC_PREPARE_FLAG) {
783 dma_unmap_sg(host->dev, data->sg, data->sg_len,
784 mmc_get_dma_dir(data));
785 data->host_cookie &= ~MSDC_PREPARE_FLAG;
811 /*DDR mode will double the clk cycles for data timeout */
1052 if (cmd->data) {
1053 struct mmc_data *data = cmd->data;
1061 rawcmd |= ((data->blksz & 0xFFF) << 16);
1062 if (data->flags & MMC_DATA_WRITE)
1064 if (data->blocks > 1)
1071 if (host->timeout_ns != data->timeout_ns ||
1072 host->timeout_clks != data->timeout_clks)
1073 msdc_set_timeout(host, data->timeout_ns,
1074 data->timeout_clks);
1076 writel(data->blocks, host->base + SDC_BLK_NUM);
1082 struct mmc_data *data)
1086 WARN_ON(host->data);
1087 host->data = data;
1088 read = data->flags & MMC_DATA_READ;
1091 msdc_dma_setup(host, &host->dma, data);
1095 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n",
1096 __func__, cmd->opcode, data->blocks, read);
1172 if (mrq->data)
1173 msdc_unprepare_data(host, mrq->data);
1228 * should not clear fifo/interrupt as the tune data
1271 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) {
1272 /* R1B or with data, should check SDCBUSY */
1325 else if (!cmd->data)
1328 msdc_start_data(host, cmd, cmd->data);
1339 if (mrq->data)
1340 msdc_prepare_data(host, mrq->data);
1356 struct mmc_data *data = mrq->data;
1358 if (!data)
1361 msdc_prepare_data(host, data);
1362 data->host_cookie |= MSDC_ASYNC_FLAG;
1369 struct mmc_data *data = mrq->data;
1371 if (!data)
1374 if (data->host_cookie) {
1375 data->host_cookie &= ~MSDC_ASYNC_FLAG;
1376 msdc_unprepare_data(host, data);
1390 struct mmc_request *mrq, struct mmc_data *data)
1403 done = !host->data;
1405 host->data = NULL;
1410 stop = data->stop;
1432 data->bytes_xfered = data->blocks * data->blksz;
1437 data->bytes_xfered = 0;
1440 data->error = -ETIMEDOUT;
1442 data->error = -EILSEQ;
1445 __func__, mrq->cmd->opcode, data->blocks);
1447 (int)data->error, data->bytes_xfered);
1520 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__);
1529 } else if (host->data) {
1530 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n",
1532 host->data->blocks);
1534 host->data);
1633 struct mmc_data *data;
1646 data = host->data;
1681 else if (data)
1682 msdc_data_xfer_done(host, events, mrq, data);
1811 /* Configure to default data timeout */
2198 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay);
2203 * MSDC IP which supports data tune + async fifo can do CMD/DAT tune
2293 dev_err(host->dev, "Tune data fail!\n");
2500 /* default write data / busy timeout 20s */
2502 /* default read data timeout 1s */