Lines Matching defs:EMMC_TOP_CONTROL
92 #define EMMC_TOP_CONTROL 0x00
289 /* EMMC_TOP_CONTROL mask */
967 host->top_base + EMMC_TOP_CONTROL);
980 host->top_base + EMMC_TOP_CONTROL);
1725 writel(0, host->top_base + EMMC_TOP_CONTROL);
1754 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1777 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1779 sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL,
1791 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1818 readl(host->top_base + EMMC_TOP_CONTROL);
1822 readl(host->top_base + EMMC_TOP_CONTROL);
2000 sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
2302 EMMC_TOP_CONTROL);
2931 readl(host->top_base + EMMC_TOP_CONTROL);
2959 host->top_base + EMMC_TOP_CONTROL);